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1. 发明专利

JP2014063771A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014063771A
公开(公告)日：2014-04-10
申请号：JP2012206195
申请日：2012-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMISAWA MASARU , ONO SHOTARO , OTA HIROSHI , YAMASHITA HIROAKI
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/407 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/402 , H01L29/66712 , H01L29/7395 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which electric field concentration on a terminal region is alleviated.SOLUTION: The semiconductor device has an element region where a semiconductor element is formed, and a terminal region surrounding the element region. The semiconductor device includes a semiconductor substrate, a trench, an insulating layer, and a field plate conductive layer. The trench is formed in the semiconductor substrate so as to surround the element region, in the terminal region. The field plate conductive layer is formed in the trench via the insulating layer.
摘要翻译：要解决的问题：提供一种减轻端子区域的电场浓度的半导体器件。解决方案：半导体器件具有形成半导体元件的元件区域和围绕元件区域的端子区域。半导体器件包括半导体衬底，沟槽，绝缘层和场板导电层。沟槽形成在半导体衬底中，以便在端子区域中包围元件区域。场板导电层经由绝缘层形成在沟槽中。

2. 发明专利

JP2012156225A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012156225A
公开(公告)日：2012-08-16
申请号：JP2011012665
申请日：2011-01-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , SAITO WATARU , TANIUCHI SHUNJI , WATANABE YOSHIO , YAMASHITA HIROAKI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, capable of reducing the manufacturing process and the cost of a super junction structure.SOLUTION: The semiconductor device includes: on a principal plane of a first semiconductor layer, a second semiconductor layer including a first conductive type first pillar and a second conductive type second pillar provided alternately and periodically in a direction parallel to the principal plane; a second conductive type first semiconductor region selectively provided on the surface of the second pillar; and a first conductive type second semiconductor region selectively provided on the surface of the first semiconductor region. In either the first pillar or the second pillar, there are provided a first buried layer and a second buried layer disposed inside a trench formed from the surface of the second semiconductor layer to the first semiconductor layer. At least one of the crystal structure and the material of the second buried layer is different from those of the first buried layer.
摘要翻译：要解决的问题：为了提供能够降低超结结构的制造工艺和成本的半导体器件及其制造方法。解决方案：半导体器件包括：在第一半导体层的主平面上，包括第一导电型第一柱和第二导电型第二柱的第二半导体层，该第二导电型第一柱与平行于该主平面的方向交替周期地设置 ; 选择性地设置在第二柱的表面上的第二导电型第一半导体区; 以及选择性地设置在第一半导体区域的表面上的第一导电类型的第二半导体区域。在第一支柱或第二支柱中，设置有第一掩埋层和第二掩埋层，该第一掩埋层和第二掩埋层设置在从第二半导体层的表面到第一半导体层形成的沟槽内。第二掩埋层的晶体结构和材料中的至少一个与第一掩埋层的晶体结构和材料不同。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2010103337A Power semiconductor device 审中-公开
标题翻译：功率半导体器件
公开(公告)号：JP2010103337A
公开(公告)日：2010-05-06
申请号：JP2008274022
申请日：2008-10-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO WATARU , ONO SHOTARO , OTA HIROSHI , YABUSAKI MUNEHISA , HATANO NANA , WATANABE MIHO
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To achieve both high speed switching and a low noise level while maintaining low on-state resistance and high avalanche resistance. SOLUTION: A power semiconductor device is characterized by comprising: a first semiconductor layer (111); second and third semiconductor layers (112, 113) formed on the first semiconductor layer, having striped forms extending in a first horizontal direction and alternately disposed in a second horizontal direction orthogonal to the first horizontal direction; a fourth semiconductor layer (114); a fifth semiconductor layer (116); a control electrode (122) formed on the second, third, fourth and fifth semiconductor layers via an insulating film; a first main electrode (123); and a second main electrode (124), wherein the control electrode includes a plane pattern which is periodic in the first and second horizontal directions and the fifth semiconductor layer is formed to have a striped form extending in the first horizontal direction and not extending in the second horizontal direction. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在保持低导通电阻和高雪崩电阻的同时实现高速开关和低噪声电平。解决方案：功率半导体器件的特征在于包括：第一半导体层（111）; 形成在第一半导体层上的第二和第三半导体层（112,113）具有在第一水平方向上延伸并交替地设置在与第一水平方向正交的第二水平方向上的条纹形状; 第四半导体层（114）; 第五半导体层（116）; 经由绝缘膜形成在所述第二，第三，第四和第五半导体层上的控制电极（122）第一主电极（123）; 和第二主电极（124），其中所述控制电极包括在所述第一和第二水平方向上是周期性的平面图案，并且所述第五半导体层形成为具有在所述第一水平方向上延伸的条纹形状，第二个水平方向。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010040857A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010040857A
公开(公告)日：2010-02-18
申请号：JP2008203297
申请日：2008-08-06
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , HARA TAKUMA , IZUMISAWA MASARU , OTA TSUYOSHI , SUGITA NAOMASA , BABA YOSHIAKI
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is low in backward leakage current and forward on voltage.
SOLUTION: The semiconductor device includes: a first semiconductor layer 11 of a first conductivity type; a second semiconductor layer 12 of a second conductivity type, which is embedded at a predetermined depth L1 from a principal surface 11a of the semiconductor layer 11 and gradually increases in cross section from the side of the principal surface 11a toward the side of the opposite surface from the principal surface 11a; a metal layer 13 which comes into contact with the principal surface 11a of the first semiconductor layer 11 to form a Schottky junction with the first semiconductor layer 11; and a high-resistance region 14 which is formed from the second semiconductor layer 12 toward the principal surface 11a of the first semiconductor layer 11 and has higher specific resistance than the first semiconductor layer 11.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种低反向泄漏电流和正向电压的半导体器件。解决方案：半导体器件包括：第一导电类型的第一半导体层11; 第二导电类型的第二半导体层12，其从半导体层11的主表面11a嵌入预定深度L1，并且从主表面11a侧朝向相对表面侧逐渐增大从主表面11a; 与第一半导体层11的主表面11a接触以与第一半导体层11形成肖特基结的金属层13; 以及由第二半导体层12朝向第一半导体层11的主面11a形成的高电阻区域14，比第一半导体层11具有更高的电阻率。（C）2010，JPO＆INPIT

5. 发明专利

JP2009272397A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009272397A
公开(公告)日：2009-11-19
申请号：JP2008120309
申请日：2008-05-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO WATARU , ONO SHOTARO , HATANO NANA , TAKASHITA MASAKATSU , OTA HIROSHI , WATANABE YOSHIO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a low ON resistance and performs large-current-density operation. SOLUTION: The semiconductor device includes: a second semiconductor layer of a first conductivity type provided on a major surface of a first semiconductor layer of the first conductivity type; and a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor layer adjacent to the second semiconductor layer, the third semiconductor layer forming a structure of periodical arrangement together with the second semiconductor layer laterally substantially parallel to the major surface of the first semiconductor layer. A portion is provided locally in the third semiconductor layer, the portion being depleted at a voltage not more than one third of a voltage at which the second semiconductor layer and the third semiconductor layer are completely depleted. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有低导通电阻并执行大电流密度操作的半导体器件。解决方案：半导体器件包括：设置在第一导电类型的第一半导体层的主表面上的第一导电类型的第二半导体层; 以及第二导电类型的第三半导体层，设置在与第二半导体层相邻的第一半导体层的主表面上，第三半导体层与第二半导体层一起形成周期性结构，该第二半导体层横向地基本平行于主表面的第一半导体层。局部地在第三半导体层中提供一部分，该部分耗尽不超过第二半导体层和第三半导体层完全耗尽的电压的三分之一的电压。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009231622A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009231622A
公开(公告)日：2009-10-08
申请号：JP2008076588
申请日：2008-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , SAITO WATARU , HATANO NANA , IZUMISAWA MASARU , SUMI YASUTO , OTA HIROSHI , SEKINE WATARU , WATANABE YOSHIO
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a superjunction region which can prevent the lowering of a breakdown voltage in a termination region, and a manufacturing method of the semiconductor device. SOLUTION: The semiconductor device comprises a super-junction region having n type pillar regions 2 and ptype pillar regions 3 alternately provided on an n+ type semiconductor substrate 1. The n and p type pillar regions 2 and 3 in a terminating region 30 have such shapes that the n and p type pillar regions 2 and 3 are alternately laminated to be parallel to the n+ type semiconductor substrate 1. An impurity concentration distribution of the n and p type pillar regions 2 and 3 in a corner 33 of the terminating region 30 has a plurality of impurity concentration peaks periodically along a curve BC bent from an x direction to a y-direction in the corner 33. Quantity of impurities in the n and p type pillar regions 2 and 3 of the corner 33 of the terminating region 30 are decreased as progressing toward outer peripheries L1 and L2 of the corner 30. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有能够防止终止区域中的击穿电压降低的超结区的半导体器件以及半导体器件的制造方法。解决方案：半导体器件包括具有交替设置在n +型半导体衬底1上的n型支柱区域2和p型柱状区域3的超结区域。终止区域30中的n型和p型型支柱区域2和3 具有这样的形状，使得n型和p型型支柱区域2和3交替地层叠以与n +型半导体衬底1平行。n端子和p型支柱区域2和3在端接部分的角部33中的杂质浓度分布区域30具有沿着从拐角33的x方向弯曲到y方向的曲线BC周期性地具有多个杂质浓度峰值。终端的角部33的n型和p型型支柱区域2和3中的杂质量区域30随着向角30的外周L1和L2的前进而减小。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2007305608A Transistor 有权
标题翻译：晶体管
公开(公告)号：JP2007305608A
公开(公告)日：2007-11-22
申请号：JP2006115456
申请日：2006-04-19
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAGAWA MITSUHIKO , NISHIMURA TAKASHI , KAWAGUCHI YUSUKE , ONO SHOTARO
IPC分类号： H01L29/786 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a transistor in which switching breakdown voltage can be assured while suppressing increase in on-resistance. SOLUTION: The transistor comprises a buried insulation layer, a semiconductor layer including a source portion having a plurality of first conductivity type source regions and a plurality of second conductivity type base contact regions arranged alternately on the major surface of the buried insulation layer, a first conductivity type drain portion, and a second conductivity type base region provided between the source portion and the drain portion in contact with the source regions and the base contact region, a gate insulating film provided on the base region, and a gate electrode provided on the gate insulating film wherein the junction of the source region and a base region is provided closer to the drain portion side than the junction of the base contact region and the base region. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在抑制导通电阻的增加的同时确保开关击穿电压的晶体管。解决方案：晶体管包括掩埋绝缘层，半导体层，包括具有多个第一导电型源极区域的源极部分和交替设置在掩埋绝缘层的主表面上的多个第二导电型基极接触区域第一导电型漏极部分和设置在与源极区域和基极接触区域接触的源极部分和漏极部分之间的第二导电型基极区域，设置在基极区域上的栅极绝缘膜和栅极电极设置在栅极绝缘膜上，其中源极区域和基极区域的接合部被设置为比基部接触区域和基底区域的接合部更靠近漏极部分侧。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007300034A Semiconductor device, and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007300034A
公开(公告)日：2007-11-15
申请号：JP2006128698
申请日：2006-05-02
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , SAITO WATARU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L2924/13055 , H01L2924/13091
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is effective for fining a pillar region, and to provide its fabrication process.
SOLUTION: The semiconductor device comprises an n-type pillar region, a p-type pillar region provided contiguously to the n-type pillar region, a base region provided on the p-type pillar region, a source region provided in the surface layer of the base region, a trench, an insulating film provided on the inner wall face of the trench, a control electrode buried in the trench through the insulating film, a source electrode, and a drain electrode. The impurity concentration in the p-type pillar region is substantially constant up to the substantially middle portion in the direction from the source electrode toward the drain electrode, and decreases gradually from the substantially middle portion toward the drain electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种对提高柱状区域有效的半导体器件，并提供其制造工艺。解决方案：半导体器件包括n型柱区域，与n型柱区域相邻设置的p型柱区域，设置在p型柱状区域上的基极区域，设置在p型柱状区域中的源极区域基底区域的表面层，沟槽，设置在沟槽的内壁面上的绝缘膜，通过绝缘膜埋入沟槽中的控制电极，源电极和漏电极。 p型柱区域中的杂质浓度在从源电极朝向漏电极的方向上的大致中间部分基本上恒定，并且从大致中部向漏电极逐渐减小。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006120894A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006120894A
公开(公告)日：2006-05-11
申请号：JP2004307852
申请日：2004-10-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having low on-resistance and more reduced in gate capacity in switching than the prior art.
SOLUTION: The semiconductor device 100 comprises an n-type semiconductor layer 10; a p-type semiconductor layer 20 formed on the semiconductor layer 10; a trench 60 that penetrates the semiconductor layer 20 from the surface of the semiconductor layer 20 to reach the semiconductor layer 10; an insulating film 70 formed on an inner wall of the trench 60; an electrode 80 formed in the trench 60 and electrically insulated from the semiconductor layers 10, 20 owing to the insulating film 70; and n-type impurity injection regions 41, 43 formed around the trench 60 in a surface region of the semiconductor layer 20, in which a profile of a portion close to the trench 60 is different from that of the other portion.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其具有比现有技术更低的导通电阻和更小的开关栅极容量。解决方案：半导体器件100包括n型半导体层10; 形成在半导体层10上的p型半导体层20; 从半导体层20的表面穿透半导体层20到达半导体层10的沟槽60; 形成在沟槽60的内壁上的绝缘膜70; 形成在沟槽60中并由于绝缘膜70而与半导体层10,20电绝缘的电极80; 以及在半导体层20的表面区域中形成在沟槽60周围的n型杂质注入区域41,43，其中接近沟槽60的部分的轮廓与另一部分的轮廓不同。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005354037A Trench mosfet 有权
标题翻译： TRENCH MOSFET
公开(公告)号：JP2005354037A
公开(公告)日：2005-12-22
申请号：JP2005112645
申请日：2005-04-08
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , NAKAGAWA AKIO , KAWAGUCHI YUSUKE , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/10 , H01L29/41 , H01L29/47 , H01L29/49 , H01L29/78 , H01L29/872 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： PROBLEM TO BE SOLVED: To provide a trench MOSFET having a Schottky diode which is small in occupation area on a semiconductor substrate, has few function impeding factors, and is built within with due regard to its cost.
SOLUTION: The trench MOSFET is equipped with a gate electrode having a trench gate structure, a gate insulating film formed so as to surround the gate electrode, an n-type diffusion layer which is formed confronting the gate electrode through the intermediary of the gate insulating film above the trench, a p-type base layer which is formed confronting the gate electrode through the intermediary of the gate insulating film at a part below the upper part of the trench, an n-type epitaxial layer which is located at a part below the above lower part of the trench, confronting the gate electrode through the intermediary of the gate insulating film, a metallic layer which is formed extending in parallel with the depth direction of the trench, separating from the trench, penetrating through the n-type diffusion layer and the p-type base layer, and reaching to the n-type epitaxial layer, and a p-type layer which is located so as to come into contact with both the p-type base layer and the metallic layer and whose impurity concentration is higher than that of the p-type base layer.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有肖特基二极管的沟槽MOSFET，其在半导体衬底上的占用面积小，具有很少的功能阻碍因素，并且在适当考虑其成本的情况下内置。解决方案：沟槽MOSFET配备有具有沟槽栅极结构的栅极电极，形成为围绕栅极电极的栅极绝缘膜，n型扩散层，其形成为通过中间的栅电极形成沟槽上方的栅极绝缘膜，在沟槽上部的一部分通过栅极绝缘膜的中间形成的p型基极层，n型外延层，其位于在沟槽的上述下部的下方的部分，通过栅极绝缘膜的中间与栅电极相对，形成为与沟槽的深度方向平行延伸的金属层，与沟槽分离，穿过n沟道型扩散层和p型基极层，并到达n型外延层，以及p型层，其位于与p型基极层和m相接触金属层，其杂质浓度高于p型基底层。版权所有（C）2006，JPO＆NCIPI

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