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1. 发明专利

JP4599375B2 Non-volatile semiconductor memory 有权
公开(公告)号：JP4599375B2
公开(公告)日：2010-12-15
申请号：JP2007186274
申请日：2007-07-17
申请人：株式会社東芝
发明人：利武八重樫 , 誠一有留 , 和裕清水 , 浩渡部 , 祐司竹内
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the resistance of a select gate electrode in a NAND cell unit. SOLUTION: In a nonvolatile semiconductor memory, each of a first and a second select gate electrodes SGD has a plurality of contact regions regularly arranged in a row direction, lies adjacent to a column direction by holding the diffusion layer or the source diffusion layer of a NAND cell unit, and extending to a row direction. The contact region of the first gate electrode and the contact region of the second select gate electrode are arranged as they are not face to each other. An interconnect wire SDL formed upper layer than the first select gate electrode is connected in the region of the first select gate electrode. The interconnect wire SDL is disposed on a memory cell in the NAND cell unit in the first select gate electrode side. COPYRIGHT: (C)2008,JPO&INPIT

2. 发明专利

JP4284311B2 A method of manufacturing a semiconductor memory device 有权
公开(公告)号：JP4284311B2
公开(公告)日：2009-06-24
申请号：JP2005290291
申请日：2005-10-03
申请人：株式会社東芝
发明人：ヘミンク・ゲルトヤン , 徹丸山 , 誠一有留 , 浩渡部
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device including finely separated electrodes which does not impart a change to operational characteristics of an element. SOLUTION: A trench 12 is formed in a semiconductor substrate 1. An isolation region 16 has a first part in which the side wall part of the trench is caused to be flush with the upper part of the trench, and a second part which protrudes from said trench at the rest part of the trench and formed with the same material as the first part. A part of an electron charge storage layer 7 on a first gate insulating film 22 is partially overlapped on said first part in the isolation region to be formed in a self-aligning manner to the second part, and has a flat top surface flush with the top surface of the second part. A second gate insulating film 8 is formed on top surfaces of the electronic charge storage layer and the second part, and a control gate 9 is formed on the second gate insulating film 8. COPYRIGHT: (C)2006,JPO&NCIPI

3. 发明专利

JP3602691B2 Non-volatile semiconductor memory device and a method of manufacturing the same 失效
公开(公告)号：JP3602691B2
公开(公告)日：2004-12-15
申请号：JP18753997
申请日：1997-06-27
申请人：株式会社東芝
发明人：誠一有留 , 和裕清水
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To suppress the film thickness of an element separating region and to increase the capacity between a floating gate and a word line, by separating the part of an isolated gate electrode having the side surface, which is self- aligned to the side end of an element isolation pattern, from a control gate electrode, and specifying the facing area of the control gate electrode and the independent electrode. SOLUTION: An active region 3 has parallel linear patterns repeatedly. In each memory cell transistor, an isolated gate electrode 5 called as a floating gate is formed. A control gate 7 is formed in linear shape connected in the row direction of a memory cell array and functions as a work line. The floating gate 5 comprises a lower part 5L whose side surface is self-aligned with the side end part of the linear pattern part of an element isolation region 2, and an upper layer part 5U whose side surface extends to the upper surface of the linear pattern part of the element isolation region 2. Since the area of the upper surface of the upper layer part 5U is larger than the area of the upper surface of the lower layer part 5L, the facing area of the floating gate 5 and the word line is larger than the self-aligning trench type.

4. 发明专利

JP3469362B2 Semiconductor memory device 失效
公开(公告)号：JP3469362B2
公开(公告)日：2003-11-25
申请号：JP16987295
申请日：1995-07-05
申请人：株式会社東芝
发明人：誠一有留
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device including a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on the semiconductor substrate. Each memory cell contains a first transistor provided with a gate, and the semiconductor substrate includes element separating trenches arranged at least in part of the respective memory cells and each of the element separating trenches is embedded at least partly with an element separating insulative film. An electrically conductive film is embedded in at least part of the remaining area of the trench, a second transistor is constructed by at least part of the lateral sides of each of the element separating trenches having an embedded conductive film forming a part of a channel region, and a third transistor is constructed by another part of the the lateral sides of each of the element separating trenches forming part of a channel region. Diffusion layers of sources and drains of the second transistor and the third transistor are shared and the second and third transistors are connected in parallel to construct the first transistor of the memory cell. The threshold voltage of the second transistor having the conductive film formed as a second gate is set to a voltage higher than a voltage applied to the second gate selected in a read operation.

5. 发明专利

JP3383428B2 Semiconductor memory device 失效
公开(公告)号：JP3383428B2
公开(公告)日：2003-03-04
申请号：JP19581194
申请日：1994-08-19
申请人：株式会社東芝
发明人：ヘミンク・ゲルトヤン , 康司作井 , 誠一有留 , 智晴田中 , 哲郎遠藤 , 晋首藤
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE: To provide a semiconductor memory device, which reduces a Vpp transistor in substrate bias effect and a enhances step-up circuit in efficiency. CONSTITUTION: An EEPROM is equipped with a P-type well 12 and an N-type well 13 both used for a peripheral circuit and formed inside a P-type substrate 11 and a P-type well 12 formed inside the memory cell N-type well 13. A memory cell transistor 18 is formed on the P-type well 12 provided inside the N-type well 13. A Vm /Vcc Nch -transistor 16 is formed on the P-type well 12, a Vm /Vcc Pch -MOS transistor 17 is formed on the N-type well 13. An Nch -transistor 15 used for a potential Vpp higher than a power supply potential is formed direct on a substrate 11 without interposing any well.

6. 发明专利

JP3382024B2 Non-volatile semiconductor memory device and a method of manufacturing the same 失效
公开(公告)号：JP3382024B2
公开(公告)日：2003-03-04
申请号：JP19582294
申请日：1994-08-19
申请人：株式会社東芝
发明人：ヘミンク・ゲルトヤン , 誠一有留
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11543
摘要： PURPOSE: To provide an EEPROM which facilitates the reduction of number of steps for mask processes for the formation of a layer-built gate, the elimination of the degradation of the reliability of a gate oxide film, improvement of the characteristics of a transistor and the reduction of the manufacturing cost of the transistor. CONSTITUTION: A cell transistor has an Si substrate 11 and first and second polycrystalline Si layers 18 and 24 built up on it. Writing and erasing are performed by the movement of electric charge between the first polycrystalline Si layer 18 and the substrate 11. A plurality of memory cell units which are respectively composed of a plurality of the connected cell transistors are arranged and connected to bit lines through selective transistors to constitute a memory cell array and peripheral circuits are provided around the memory cell array to constitute an EEPROM. The selective transistors and the transistors of the peripheral circuits have, like the cell transistors, gates composed of the layer-built first and second polycrystalline Si layers 18 and 24 and the first and second polycrystalline Si layers 18 and 24 are partially brought into contact with each other.

7. 发明专利

JP3959165B2 Non-volatile semiconductor memory device 失效
公开(公告)号：JP3959165B2
公开(公告)日：2007-08-15
申请号：JP32594597
申请日：1997-11-27
申请人：株式会社東芝
发明人：誠一有留 , 和裕清水
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/822 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/8221 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/1203 , H01L29/7881
摘要： A NAND type EEPROM according to the present invention is formed on an SOI substrate as follows. Silicon thin films (element regions) isolated in a grid pattern are formed on an insulation layer on a silicon substrate. A trench between the silicon thin films is filled with insulating material. Thus, the elements in the row direction are isolated completely by the insulating material. A silicon thin film on which a memory cell is formed, contains a very small amount of n-type impurities and is close to an intrinsic semiconductor. A silicon thin film on which a select gate transistor is formed is of a p-type. The source and drain diffusion layers of the memory cell and select gate transistor are of an n-type. The channel of each of memory cells constituting a NAND string is constituted of at least two regions having different threshold voltages.

8. 发明专利

JP3895816B2 And control method thereof nonvolatile semiconductor memory device, a memory card, and the storage system 失效
公开(公告)号：JP3895816B2
公开(公告)日：2007-03-22
申请号：JP34519596
申请日：1996-12-25
申请人：株式会社東芝
发明人：誠一有留
IPC分类号： G11C16/02 , G11C16/04 , G11C16/10 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device includes a memory cell array having a plurality of pages, each page being formed of a plurality of memory cells connected to one word line, and serving as the data write unit, and a plurality of blocks formed of a plurality of pages, and a controller for selecting any one of the plurality of blocks, selecting any one of pages in the selected block, erasing data stored in the selected page, and then writing new data in the selected page, while reading data stored in non-selected pages within the selected block, storing the data in a buffer memory outside the memory cell, a dedicated buffer memory in the memory cell, or an unused block in the memory cell, performing a data erase, and rewriting the data stored in the buffer memory or unused block.

9. 发明专利

JP3878374B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP3878374B2
公开(公告)日：2007-02-07
申请号：JP34235899
申请日：1999-12-01
申请人：株式会社東芝
发明人：直井口 , 国博寺坂 , 直樹小井土 , 一仁成田 , 誠一有留 , 和裕清水 , 理一郎白田 , 弘昭角田 , 裕久飯塚
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 mum or less, and a gate length of a memory cell is 0.2 mum or less.

10. 发明专利

JP3641103B2 Method of manufacturing a non-volatile semiconductor memory device 失效
公开(公告)号：JP3641103B2
公开(公告)日：2005-04-20
申请号：JP17245097
申请日：1997-06-27
申请人：株式会社東芝
发明人：誠一有留 , 栄二神谷
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is left in order to insulate drain diffusion layers of cell transistors in the row direction from each other when contacts of a memory cell group are subjected to PEP. Using the island-like resist patterns as masks, contact holes communicating with both the drain diffusion layers and source diffusion layers are made. Since, therefore, drain and source contact holes are arranged in matrix, the PEP margin can greatly be increased, thereby making it possible to prevent the problems of forming no contact holes and causing a short circuit between the gate and contact from arising.

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