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3. 发明专利

JP4343294B2 Non-volatile memory device and a method for manufacturing the same 有权
公开(公告)号：JP4343294B2
公开(公告)日：2009-10-14
申请号：JP30299198
申请日：1998-10-23
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：仁善朴 , 鐘鎬李 , 次英柳
IPC分类号： H01L21/8246 , H01L27/108 , G11C11/22 , H01L21/8242 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a silicon-on-insulator substrate having a handling wafer, a first insulating layer, and a semiconductor layer. It also includes a first conductive layer used as a bit line formed in the first insulating layer, a source region formed in the semiconductor layer, a drain region formed in the semiconductor layer, a second insulating layer formed over the semiconductor layer between the source and drain regions, a second conductive layer for use as both a lower electrode and gate electrode, formed over the second insulating layer between the source and drain regions, a ferroelectric layer formed over the semiconductor layer, and a third conductive layer for use as an upper electrode formed over the ferroelectric layer. For reading, writing, and erasing, different voltages are applied to the upper electrode and the semiconductor layer between the drain and source. For writing, the upper electrode receives a writing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state to either invert polarization of the ferroelectric layer or retain initial polarization, depending upon the data. For erasing, the upper electrode receives an erasing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state. For reading, the upper electrode receives a reading voltage, and the semiconductor layer receives a ground voltage. A sensing current is then provided to the drain, and potential variation is sensed on the bit line.

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