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1. 发明专利

JP2004153038A Circuit device and its manufacturing method 审中-公开
公开(公告)号：JP2004153038A
公开(公告)日：2004-05-27
申请号：JP2002317086
申请日：2002-10-31
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： SAKAMOTO HIROYUKI , ISHIKAWA KAZUYA , YOKOYAMA SEIICHI
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31
CPC分类号： H01L23/3135 , H01L23/293 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/181 , H01L2924/3025 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a circuit device which hardly has a crack in a substrate, a glaze layer, or a semiconductor chip and causes no sagging in a sealing layer. SOLUTION: The device has the substrate, the semiconductor chip mounted on the substrate, and the sealing layer covering the semiconductor chip for sealing. The sealing layer has a silicone-based material. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2014220287A 樹脂封止品及び樹脂封止品の製造方法审中-公开
标题翻译：树脂密封产品和制造树脂密封产品的方法
公开(公告)号：JP2014220287A
公开(公告)日：2014-11-20
申请号：JP2013096748
申请日：2013-05-02
申请人：アルプス電気株式会社 , Alps Electric Co Ltd
发明人： ISHIKAWA KAZUYA , KITAURA NAOKI , SHIBUYA YOSHIHISA , CHIBA KAZUYOSHI , SUGAWARA TAKESHI
IPC分类号： H01L23/12 , H01L21/56
CPC分类号： H01L24/97 , H01L21/565 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00
摘要：【課題】小型化に適した樹脂封止品及び樹脂封止品の製造方法を提供する。【解決手段】基板20に実装された電子部品により電子回路を形成し、この電子回路と電気的に接続するための電極40が基板20の側面20aに露出され、基板20の上面20bは電極40の上面側40a及び前記電子部品を封止するよう樹脂50により覆われている樹脂封止品1であって、電極40は基板20の側面20aから凹状に窪んだ溝部25を形成しているとともに、溝部25において、電極40の下方側40cが拡開されており、電極40の上方側40bは樹脂50により前記溝部に沿って封止されて、電極40の下方側40cのみが露出されている。【選択図】図1
摘要翻译：要解决的问题：提供一种适用于压实的树脂密封产品，并提供一种制造树脂密封产品的方法。解决方案：在由安装在基板20上的电子部件形成电子电路的树脂密封产品1中将与电子电路电连接的电极40暴露于基板20的侧面20a，并且用树脂50覆盖基板20的上表面20b，以密封基板20的上表面侧40a 电极40和电子部件。电极40形成从基板20的侧面20a凹陷的槽25.在槽25中，电极40的下侧40c膨胀，电极40的上侧40b沿树脂50密封凹槽，并且仅暴露电极40的下侧40c。

3. 发明专利

JP2007013001A Electronic circuit unit and its manufacturing method 审中-公开
标题翻译：电子电路单元及其制造方法
公开(公告)号：JP2007013001A
公开(公告)日：2007-01-18
申请号：JP2005194075
申请日：2005-07-01
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA
IPC分类号： H05K3/34 , H01L21/60 , H05K1/18
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit unit which has no positional displacement between electronic circuit components and uses an inexpensive reflow device, and also to provide a method for manufacturing the unit. SOLUTION: The electronic circuit unit or the method for manufacturing the unit comprises solder bumps 3 formed on first lands 2a of a circuit board 1, an electronic circuit component 5 soldered by the solder bumps 3, and solder terminals 4 provided to second lands 2b of the circuit board 1. Since the solder bump 3 is made of melted mixture solder containing a first solder material and a second solder material higher in melting temperature than the first solder material, the melting temperature of the solder bump 3 is higher than that of the first solder material. Consequently, when the reflow device is set at a temperature at which the solder bump 3 is not melted, the solder bump 3 can be prevented from being melted, the position displacement can be avoided between the electronic circuit components 5, the reflow device can be simplified and made inexpensive. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种电子电路单元，其在电子电路部件之间没有位置偏移并且使用廉价的回流装置，并且还提供用于制造该单元的方法。电子电路单元或其制造方法包括形成在电路板1的第一焊盘2a上的焊料凸起3，由焊料凸块3焊接的电子电路部件5以及设置在第二焊盘4上的焊接端子4 由于焊锡凸块3由含有比第一焊料材料更高熔点的第一焊料材料和第二焊料材料的熔融混合焊料制成，焊料凸点3的熔化温度高于第一种焊料材料。因此，当回流装置设定在焊料凸块3不熔化的温度时，可以防止焊料凸点3熔化，可以避免电子电路部件5之间的位置偏移，回流装置可以简化，便宜。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007005559A Electronic circuit module 审中-公开
标题翻译：电子电路模块
公开(公告)号：JP2007005559A
公开(公告)日：2007-01-11
申请号：JP2005183785
申请日：2005-06-23
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit module which does not damage reliability even if it is subjected to heating treatment after being mounted on a mother board. SOLUTION: The electronic circuit module 10 is mainly constituted of a bare chip 11, a plurality of connection bumps 12 disposed in the circumferential edge of the bottom surface of the bare chip 11, an intermediate substrate 13 which is a ceramic system substrate wherein the bare chip 11 is subjected to flip-chip packaging in a top surface, a spacer 14 interposed in almost a central part between the bare chip 11 and the intermediate substrate 13, and an underfiller 15 consisting of a resin material filled in a circumferential edge between the bare chip 11 and the intermediate substrate 13. The spacer 14 is formed of a material whose thermal expansion coefficient is smaller enough than that of the underfiller 15, preferably silicon or ceramic. The electronic circuit module 10 is used as mounted on the mother board 20, and the bare chip 11 is connected to the mother board 20 via the intermediate substrate 13. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种即使在安装在母板上进行加热处理后也不会损坏可靠性的电子电路模块。电解电路模块10主要由裸芯片11，设置在裸芯片11的底面的周缘的多个连接凸块12，作为陶瓷系统基板的中间基板13 其中裸芯片11在顶表面进行倒装芯片封装，插入介于裸芯片11和中间基板13之间的中心部分的间隔件14以及填充有周向的树脂材料的底部填充物15 边缘在裸芯片11和中间基板13之间。间隔件14由热膨胀系数小于底部填充物15的材料形成，优选为硅或陶瓷。电子电路模块10被安装在母板20上，裸芯片11经由中间基板13连接到母板20.版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008004757A Mounting structure of semiconductor component, and mounting board used for it 审中-公开
标题翻译：半导体元器件的安装结构以及安装板
公开(公告)号：JP2008004757A
公开(公告)日：2008-01-10
申请号：JP2006172754
申请日：2006-06-22
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA , KODERA YASUO
IPC分类号： H01L21/60 , H01L23/12 , H05K3/34
CPC分类号： H01L2224/14
摘要： PROBLEM TO BE SOLVED: To provide a small mounting structure of a semiconductor component capable of increasing a banking up amount of a solder, and to provide a mounting board used for it. SOLUTION: An opposed part 6a mutually facing on a second line S2 is provided with mutually adjacent land parts 6 arranged on a first line S1 in a parallel direction in the mounting structure of the semiconductor component. This can increase an area of the land part 6 to increase the amount of the solder banking up part 9, decreasing an interval between the land parts 6, which increases the density and provides a small mounting structure. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够增加焊料的堆积量的半导体部件的小型安装结构，并提供用于其的安装板。解决方案：在第二线S2上相互面对的相对部分6a在半导体部件的安装结构中设置有沿平行方向布置在第一线S1上的彼此相邻的脊部6。这可以增加焊盘部分6的面积以增加焊料堆积部分9的数量，从而减小焊盘部分6之间的间隔，这增加了密度并提供了小的安装结构。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2005229002A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005229002A
公开(公告)日：2005-08-25
申请号：JP2004037598
申请日：2004-02-16
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a low cost semiconductor device having a satisfactory insulation in the vicinity of an electrode of a semiconductor chip, and to provide its manufacturing method.
SOLUTION: The semiconductor device comprises a semiconductor chip 1 with a plurality of electrodes 2 provided; an insulating film 4 having a plurality of conductive patterns 5 connected to the electrode 2; and a bump 6 comprising a solder filled in a hole 4a provided in the insulating film 4 and connected to the conductive pattern 5. An insulating film 3 having an insulating film removing part 3a is provided beneath the undersurface of the semiconductor chip 1, and the insulating film 4 is provided beneath the undersurface of the semiconductor chip 1 with the conductive pattern 5 positioned in the insulating film removing part 3a. An intervenient of the insulating film 3 between the conductive patterns 5 positioned and adjacent each other in the vicinity of at least the electrode 2 steadily insulates between the thicken electrodes 2 or between the conductive patterns 5 positioned in the vicinity of it to be able to provide a high quality semiconductor device.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在半导体芯片的电极附近具有令人满意的绝缘性的低成本半导体器件，并提供其制造方法。解决方案：半导体器件包括具有多个电极2的半导体芯片1; 具有连接到电极2的多个导电图案5的绝缘膜4; 以及凸块6，其包括填充在设置在绝缘膜4中并连接到导电图案5的孔4a中的焊料的焊料6.具有绝缘膜去除部分3a的绝缘膜3设置在半导体芯片1的下表面的下方，绝缘膜4设置在半导体芯片1的下表面下方，导电图案5位于绝缘膜去除部分3a中。至少电极2附近位于彼此相邻的导电图案5之间的绝缘膜3的介入部分在增厚电极2之间或位于其附近的导电图案5之间稳定地绝缘，从而能够提供高品质的半导体器件。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2011228322A Electronic circuit module manufacturing method and electronic circuit module 审中-公开
标题翻译：电子电路模块制造方法和电子电路模块
公开(公告)号：JP2011228322A
公开(公告)日：2011-11-10
申请号：JP2010093676
申请日：2010-04-15
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA , MIYAURA MASAO
IPC分类号： H01L21/56 , H01L23/00 , H01L23/28 , H01L23/29 , H01L23/31
CPC分类号： H01L23/552 , H01L21/6836 , H01L24/97 , H01L2221/68327 , H01L2224/16225 , H01L2224/97 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2224/81 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a technique permitting sufficient shielding of side faces of a circuit board even where individual electronic circuit modules are to be manufactured from a collective substrate.SOLUTION: An electronic circuit module manufacturing method comprises a pasting step S100 to paste the under face of a collective substrate 20 to a groove forming dicing tape 30, a groove forming step S110 to form a groove 16 among a sealing resin layer 13, a circuit board 11 and the groove forming dicing tape 30 by cutting the sealing resin layer 13 and the circuit board 11 along a prospective separation line 15 from the upper face side of the collective substrate 20 and cutting off part of the groove forming dicing tape 30, a shield layer forming step S120 to form a shield layer 14 of an electroconductive resin over the upper face and side faces of the sealing resin layer 13 and side faces of the circuit board 11 by filling the groove 16 with the electroconductive resin, and a fragmenting step S130 to fragment a plurality of electronic circuit modules 10 arrayed over the collective substrate 20 as individual electronic circuit modules.
摘要翻译：要解决的问题：即使在从集体基板制造各个电子电路模块的情况下，也可以提供允许电路板侧面充分屏蔽的技术。解决方案：一种电子电路模块制造方法，包括：将集合基板20的下表面粘贴到槽形成切割带30上的粘贴步骤S100，形成沟槽的步骤S110，以在密封树脂层13中形成凹槽16 ，电路板11和槽形成切割带30，通过从集合基板20的上表面侧沿着预期分离线15切割密封树脂层13和电路板11，并切断槽形成切割带的一部分 30是屏蔽层形成步骤S120，通过用导电树脂填充槽16，在密封树脂层13和电路板11的侧面的上表面和侧面上形成导电树脂的屏蔽层14，以及分段步骤S130，将作为单独的电子电路模块排列在集体基板20上的多个电子电路模块10分段。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2008021955A Circuit board, circuit board with solder and method for manufacturing the same, and semiconductor component mounting board and method for manufacturing the same 审中-公开
标题翻译：电路板，具有焊接件的电路板及其制造方法以及半导体元件安装板及其制造方法
公开(公告)号：JP2008021955A
公开(公告)日：2008-01-31
申请号：JP2006294335
申请日：2006-10-30
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： ISHIKAWA KAZUYA
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a circuit board for achieving miniaturization and highly dense wiring, and for forming a solder section whose buildup is high, and for surely mounting semiconductor components, and to provide a circuit board with solder using the above mentioned circuit board and a semiconductor component mounting substrate and a method for manufacturing them.
SOLUTION: A land part 3 extended from a leader conductor 2 is configured of a plurality of thin conductor patterns 3a separated to the width direction by a solder non-adhesion section 3b formed between both sides 3d and 3d with fixed width between the both sides 3d and 3d and one wide conductor pattern 3c which is not separated by the solder non-adhesion section 3b in the extended direction. In the case of applying cream solder 8 to the land section 3, and heating and melting it to form a solder part 5, the solder part 5 whose buildup is high is formed by making solder agglomerate in the wide conductor pattern 3c with the surface tension of the melted solder.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于实现小型化和高密度布线的电路板，以及用于形成堆积高的焊料部分，并且用于可靠地安装半导体部件，并且使用上述方法为电路板提供焊料上述电路板和半导体元件安装基板及其制造方法。解决方案：从引导导体2延伸的陆部3由通过形成在两侧3d和3d之间的焊料非粘附部分3b而在宽度方向上分开的多个细导体图案3a构成，其间具有固定的宽度两侧3d和3d以及一个宽的导体图案3c，其不被焊料非粘附部分3b在延伸方向上分离。在将霜状焊料8涂敷到焊盘部3的情况下，通过加热熔融而形成焊料部5，通过使具有表面张力的宽导体图案3c中的焊料聚集体形成积层高的焊料部5 的熔化焊料。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007335653A Circuit board, method of manufacturing the same, and circuit module using the same 审中-公开
标题翻译：电路板及其制造方法和使用该电路板的电路模块
公开(公告)号：JP2007335653A
公开(公告)日：2007-12-27
申请号：JP2006166147
申请日：2006-06-15
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： SUZUKI NOBUYUKI , ISHIKAWA KAZUYA
IPC分类号： H05K3/46 , H05K3/28
CPC分类号： H01L2224/81193
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive circuit board, a method of manufacturing the circuit board in simple manufacturing steps, and a circuit module using the circuit board. SOLUTION: In the method of manufacturing the circuit board, when a press step is carried out for stacking a first green sheet 13 having a through-hole 2a provided therein, and a second green sheet 14 having a conductor 6 provided thereon and pressing the laminate, the conductor 6 enters the through-hole 2a so that an electrode 7 is formed to be flush with the exposure surface of the first green sheet 13. Consequently, the manufacture is simple and requires a less number of manufacturing steps, and thus the circuit board can be made inexpensive. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种廉价的电路板，简单制造步骤中制造电路板的方法和使用该电路板的电路模块。解决方案：在制造电路板的方法中，当进行压制步骤以堆叠具有设置在其中的通孔2a的第一生片13和设置有导体6的第二生片14时，按压层压体，导体6进入通孔2a，使得电极7形成为与第一生片13的暴露表面齐平。因此，制造简单并且需要较少数量的制造步骤，并且因此可以使电路板便宜。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2005228909A Method of manufacturing ceramic wafer 审中-公开
标题翻译：陶瓷制造方法
公开(公告)号：JP2005228909A
公开(公告)日：2005-08-25
申请号：JP2004036071
申请日：2004-02-13
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： YOKOYAMA SEIICHI , ISHIKAWA KAZUYA , SAKAMOTO HIROYUKI
IPC分类号： B28D5/02 , H01L21/301 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing ceramic wafers, with which accurate scribe grooves can be formed, the service life of a cutting blade portion can be prolonged, and yield is improved. SOLUTION: In a method of manufacturing a ceramic wafer, two linear edges 6a, 6b perpendicular to each other are provided at an outer edge of a disk-like ceramic wafer 6; scribe grooves are formed on an upper surface of the ceramic wafer 6 from positions of the two linear edges 6a, 6b by a cutting blade portion 5; the ceramic wafer is then divided into four along with the scribe grooves to form divided wafers 7; and scribe grooves are then formed from linear divided edges 7a, 7b perpendicular to each other to the divided wafers 7 by the cutting blade 5. Thus, the scribe grooves are provided from the two linear edges 6a, 6b and the divided edges 7a, 7b, thereby eliminating deviation of the cutting blade portion at the edges, and forming accurate scribe grooves. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种制造陶瓷晶片的方法，通过该方法可以形成精确的划线槽，可以延长切割刀片部分的使用寿命，并且提高产量。解决方案：在制造陶瓷晶片的方法中，在盘状陶瓷晶片6的外边缘处设置彼此垂直的两个线性边缘6a，6b; 通过切割刀片部5从两个线性边缘6a，6b的位置在陶瓷晶片6的上表面上形成划线槽; 然后将陶瓷晶片与划线槽一起分成四个，以形成分开的晶片7; 然后通过切割刀片5将由分割的晶片7彼此垂直的线性分割边缘7a，7b形成划线槽。因此，划线槽由两个线性边缘6a，6b和分割边缘7a，7b提供从而消除切割刀片部分在边缘处的偏差，并形成精确的划线槽。版权所有（C）2005，JPO＆NCIPI

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