专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005197521A Semiconductor manufacturing system and work manufacturing system 审中-公开
标题翻译：半导体制造系统和工作制造系统
公开(公告)号：JP2005197521A
公开(公告)日：2005-07-21
申请号：JP2004003269
申请日：2004-01-08
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： OKADA YOSHIO , KOIKE ATSUYOSHI , WAKABAYASHI TAKAYUKI
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To markedly improve the productivity of a semiconductor device by preventing the stagnation of manufacture of the semiconductor device in a flow shop.
SOLUTION: A semiconductor manufacturing system 1 in a clean room consists of the combination of a flow shop 2 and a job shop 3. The flow shop 2 consists of a pseudo flow shop 4 and a pseudo job shop 5. In the pseudo flow shop 4, manufacturing apparatuses where productivity can be balanced taking the difference of the throughput of the manufacturing apparatuses into consideration are arranged respectively. In the pseudo job shop 5, manufacturing apparatuses where productivity can not be balanced including the manufacturing apparatuses of low and high throughput are arranged respectively, and are shared with the pseudo flow shop 4. Thus, the difference of the throughput of the manufacturing apparatuses is reduced to markedly reduce a cycle time.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过防止半导体器件在流动车间中的制造停滞来显着提高半导体器件的生产率。解决方案：洁净室中的半导体制造系统1由流动车间2和作业车间3的组合组成。流动车间2由伪流动车间4和伪作业车间5组成。在假的流动车间4分别布置考虑了制造装置的生产能力的差异而能够平衡生产率的制造装置。在伪作业车间5中，分别配置具有低通过量和高通量的制造装置的生产率不能平衡的制造装置，并与伪流程车间4共享。因此，制造装置的生产量的差异为减少以显着缩短循环时间。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005197500A Semiconductor manufacturing system, manufacturing method of semiconductor device, work manufacturing system, and manufacturing method of work 审中-公开
标题翻译：半导体制造系统，半导体器件的制造方法，工作制造系统和制造工艺方法
公开(公告)号：JP2005197500A
公开(公告)日：2005-07-21
申请号：JP2004002851
申请日：2004-01-08
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： TAKEHARA NAOKI , KOIKE ATSUYOSHI , OKADA YOSHIO , WAKABAYASHI TAKAYUKI
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a technology of considerably improving the productivity of semiconductor devices by preventing stagnation of semiconductor device manufacturing in a flow shop. SOLUTION: A semiconductor manufacturing system 1 is provided with a pseudo flow shop 3, and a pseudo job shop 4. The pseudo flow shop 3 comprises cells 3a, 3b each including a group of manufacturing apparatuses which is a required minimum unit in a manufacturing process flow; and each manufacturing apparatus is well-balanced for the productivity by taking into account factors such as the processing capability, frequency of maintenance, maintenance time, frequency of occurrence of failures, and a difference from repair times in each manufacturing apparatus. Cell hosts 5, 11 are respectively provided on the cells 3a, 3b and respectively control the cells 3a, 3b as independent manufacturing lines. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过防止流动车间中的半导体装置制造的停滞而显着提高半导体装置的生产率的技术。解决方案：半导体制造系统1设置有伪流动车间3和伪作业车间4.伪流动车间3包括单元3a，3b，每个单元3a，3b包括一组制造设备，其是要求的最小单位制造工艺流程; 并且通过考虑处理能力，维护频率，维护时间，故障发生频率以及每个制造装置中的修理时间的差异等因素，每个制造装置的生产率平衡良好。细胞宿主5,11分别设置在细胞3a，3b上，分别控制细胞3a，3b作为独立的生产线。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005174049A Confidential information management system and confidential information management method 审中-公开
标题翻译：机密信息管理系统和机密信息管理方法
公开(公告)号：JP2005174049A
公开(公告)日：2005-06-30
申请号：JP2003414212
申请日：2003-12-12
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： TERASAWA TAKESHI , TADA NAOTSUYO , BESSHO HIROMI
IPC分类号： G06F12/14 , G06F1/00 , G06F12/00 , G06F15/00 , G06F21/00 , G06F21/60 , G06F21/64 , G06Q10/00 , G06Q50/00 , G06Q50/16 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To provide a confidential information management system and a confidential information management method, capable of preventing unjust bringing-out of an electronic file by bringing-in of a laptop PC or the like. SOLUTION: The inside of the PC is provided with: a system date change detection part 1a preventing an unjust change of a system date of the PC; a file update detection processing part 1b detecting a generation date, and a path name and a file name or the like of the electronic file are detected when new production or update of the electronic file is generated, and cumulatively storing them in a storage medium 1e as a record of an event; an update file list output processing part 1c displaying the stored record of the event on an output display part 1f; and a approval confirmation processing part 1d or the like inquiring of a management responsible person or the like of information whether approving the displayed record of the event or not. Thereby, only the approved electronic file can be brought out. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种机密信息管理系统和机密信息管理方法，能够通过引入膝上型PC等来防止电子文件的不正当引出。解决方案：PC内部设置有：防止PC的系统日期的不正确变更的系统日期变更检测部1a; 检测生成日期的文件更新检测处理部分1b以及电子文件的新的生成或更新生成时的电子文件的路径名称和文件名称等，并将它们累积地存储在存储介质1e中作为事件的记录; 在输出显示部1f上显示存储的事件记录的更新文件列表输出处理部1c; 以及向管理负责人等询问是否批准所显示的事件的记录的信息的批准确认处理部1d等。因此，只能批准电子文件。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005135117A Production planning support system, production planning method, and manufacturing method of semiconductor device 审中-公开
标题翻译：生产计划支持系统，生产计划方法和半导体器件的制造方法
公开(公告)号：JP2005135117A
公开(公告)日：2005-05-26
申请号：JP2003369754
申请日：2003-10-30
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： TAKEHARA NAOKI , OKABE TSUTOMU
IPC分类号： G05B19/418 , G06Q50/00 , G06Q50/04 , G06F17/60
CPC分类号： Y02P90/14 , Y02P90/20 , Y02P90/30
摘要： PROBLEM TO BE SOLVED: To provide a technique that can shorten a cycle time by accumulating, evaluating and verifying lot assignment rules and applying optimum assignment rules, in production planning. SOLUTION: A production planning support system has a production management information part 14 for storing information on production management (product delivery dates, progress, costs, processes and the like), a device management information part 15 for storing information on device management (processing device states, processing conditions and the like), and an operation part (hit rate operation part 19) for calculating a degree of matching (hit rate) between the information in the production management information part 14 or/and device management information part 15, assignment information obtained from assignment rules (information in a processing candidate list storage part 161), and information about actual instructions by persons for processing devices and processing sequences (information in a processing instruction result storage part 171). COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以通过在生产计划中累积，评估和验证批次分配规则并应用最佳分配规则来缩短周期时间的技术。
解决方案：生产计划支持系统具有用于存储关于生产管理（产品交付日期，进度，成本，处理等）的信息的生产管理信息部分14，用于存储关于设备管理的信息的设备管理信息部分15 （处理装置状态，处理条件等）以及用于计算生产管理信息部分14中的信息或/和装置管理信息部分之间的匹配程度（命中率）的操作部分（命中率操作部分19） 15，从分配规则获得的分配信息（处理候选列表存储部161中的信息）以及关于处理装置的人员的实际指示和处理顺序的信息（处理指示结果存储部171中的信息）。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005079491A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005079491A
公开(公告)日：2005-03-24
申请号：JP2003311007
申请日：2003-09-03
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： AKAMATSU SHIRO , EGAWA YUICHI , FUKAMI AKIRA , OHARA HIROYUKI
IPC分类号： H01L21/66 , H01L21/3205 , H01L21/82 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which the repair of a defect of a wiring pattern can be made efficiently.
SOLUTION: A wiring pattern is formed on a semiconductor wafer (S101). Subsequently, visual inspection on the formed wiring pattern is carried out (S102). The visual inspection is performed by comparing wiring patterns between neighboring cells. Next, the kind of the defect detected by the visual inspection is discriminated (S103). The discrimination of the kind of the defect is carried out in such a way that a designed layout pattern and an actual wiring pattern are subdivided, and whether the defect is a short-circuit defect or a disconnection defect is discriminated by comparing whether a pattern exists or not in a subdivided region of the layout pattern and whether a pattern exists or not in the corresponding subdivided region of the wiring pattern. Then, the discriminated defect of the short-circuit type or the disconnection type is repaired as required. The repair is carried out by a photolithography technology using an electron-beam exposure apparatus and an etching technology.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，通过该方法可以有效地进行布线图案的缺陷的修复。解决方案：在半导体晶片上形成布线图案（S101）。随后，对形成的布线图案进行目视检查（S102）。通过比较相邻单元之间的布线图案来进行目视检查。接下来，判别通过目视检查检测到的缺陷的种类（S103）。对缺陷的种类进行区分，使得设计的布图图案和实际的布线图案被细分，通过比较图案是否存在来区分缺陷是短路缺陷还是断开缺陷或者不在布局图案的细分区域中，以及在布线图案的相应细分区域中是否存在图案。然后，根据需要修复短路型或断路型的鉴别缺陷。通过使用电子束曝光装置和蚀刻技术的光刻技术进行修复。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005057200A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005057200A
公开(公告)日：2005-03-03
申请号：JP2003289059
申请日：2003-08-07
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： MANAKA AKIKO , SASAKI YASUSHI , HOSHI HATSUMI
IPC分类号： G01R31/26 , H01L21/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a technology by which failure processes caused by a defect are detected regardless of chip sizes.
SOLUTION: On the Basis data where particles or pattern defects on a semiconductor wafer are detected per unit chip in each manufacturing process P1 to P35 to fabricate circuits on the semiconductor wafer per unit chip, and data where respective conforming and nonconforming chips completed through each manufacturing process P1 to P35 are discriminated by an electric inspection in a probe inspection process P36, a yield loss of each manufacturing process P1 to P35 is computed using a kill ratio computing method, then a manufacturing process which causes the particles or the pattern defects is detected from the yield loss of each manufacturing process P1 to P35, wherein several chips are gathered and an imaginary chip size is obtained, and the yield loss of each manufacturing process P1 to P35 is obtained from a KR (Kill Ratio) value calculated using the imaginary chip size.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种由芯片尺寸来检测由缺陷引起的故障处理的技术。
解决方案：根据每个制造工序P1〜P35中每单位芯片检测到半导体晶片上的颗粒或图案缺陷的基础数据，以制造每单位芯片上的半导体晶片上的电路，以及完成各自符合和不合格芯片的数据通过各检测处理P36中的电检查来判定各制造工序P1〜P35，使用杀死率计算法计算各制造工序P1〜P35的屈服损失，然后进行使粒子或图案从各制造工序P1〜P35的屈服损失中检测到缺陷，其中收集了几个芯片并获得了虚设的芯片尺寸，并且从计算的KR（杀死率）值获得了每个制造过程P1至P35的屈服损失使用假想的芯片大小。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005050941A Semiconductor device, its manufacturing method, image sensor, and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法，图像传感器及其制造方法
公开(公告)号：JP2005050941A
公开(公告)日：2005-02-24
申请号：JP2003204201
申请日：2003-07-31
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： FUKAMI AKIRA , EGAWA YUICHI , AKAMATSU SHIRO , OHARA HIROYUKI
IPC分类号： H01L21/66 , H01L21/8244 , H01L27/11 , H01L27/14 , H01L27/146
摘要： PROBLEM TO BE SOLVED: To provide technology obtaining characteristic information of a photodiode cell constituting a CMOS (complementary metal oxide semiconductor) image sensor in a TEG (test element group) cell. SOLUTION: In the image sensor arranging a plurality of arrays and arranging a plurality of the photodiode cells DS in each of the plurality of the arrays in the form of a matrix, one from among the plurality of the photodiode cells DS is replaced with the TEG cell TS1, and an element of the substantially same shape as an element constituting the photodiode cell DS is formed into the TEG cell TS1. The photodiode cell DS does not exist at an originally existing position by being replaced with the TEG cell TS1, and the image lacks, but it is complemented with image data of the photodiode cells DS(A)-DS(H) adjoined with the TEG cell TS1 allowing the lack. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供在TEG（测试元件组）单元中获得构成CMOS（互补金属氧化物半导体）图像传感器的光电二极管单元的特性信息的技术。解决方案：在图像传感器中排列多个阵列并且以矩阵的形式将多个阵列中的每一个阵列中的多个光电二极管单元DS布置成多个光电二极管单元DS中的一个，与TEG单元TS1形成，并且与构成光电二极管单元DS的元件基本相同形状的元件形成为TEG单元TS1。光电二极管单元DS通过用TEG单元TS1替代而不存在于最初存在的位置，并且图像缺少，但是与TEG相邻的光电二极管单元DS（A）-DS（H）的图像数据相互补充细胞TS1允许缺乏。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005005516A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005005516A
公开(公告)日：2005-01-06
申请号：JP2003167856
申请日：2003-06-12
申请人： Renesas Technology Corp , Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社 , 株式会社ルネサステクノロジ
发明人： SHOJI KENICHI , YOSHIDA SEIJI , MORIMOTO KENICHI , SATO YASUO , TANAKA HIDEKI , OSAKA HIROAKI , YAMAMOTO HIROHIKO , NAKAMINE TOMOYASU , IMAMURA TOSHIHIRO , SUZUKI TADASHI
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve write characteristic of a nonvolatile memory cell, to improve reliability of a gate insulating film of an field effect transistor included in a logic circuit, and also to provide a method of manufacturing the semiconductor device which can reduce the number of processes and improve reliability. SOLUTION: After a gate insulating film 7, a polysilicon film 8, a silicon oxide film 9, and a silicon nitride film 10 are sequentially formed on a semiconductor substrate 1; these films are left only on the nonvolatile memory cell forming region using the photolithography and etching technologies. Subsequently, a gate insulating film 13a is formed with an ISSG oxide method, and simultaneously a silicon oxide film 14 is formed on the silicon nitride film 10 of the nonvolatile memory cell forming region. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够提高非易失性存储单元的写入特性的半导体器件，提高包含在逻辑电路中的场效应晶体管的栅极绝缘膜的可靠性，并提供一种方法制造可以减少工艺数量并提高可靠性的半导体器件。解决方案：在栅极绝缘膜7之后，在半导体衬底1上依次形成多晶硅膜8，氧化硅膜9和氮化硅膜10; 这些膜仅使用光刻和蚀刻技术留在非易失性存储单元形成区域上。随后，用ISSG氧化物法形成栅极绝缘膜13a，同时在非易失性存储单元形成区域的氮化硅膜10上形成氧化硅膜14。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004363288A Manufacturing method and inspection system for semiconductor device 审中-公开
公开(公告)号：JP2004363288A
公开(公告)日：2004-12-24
申请号：JP2003159290
申请日：2003-06-04
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： SAEKI KEIICHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a technique for promoting automatization and reducing the cycle time, product TAT (Turn Around Time), and working manpower in executing a sample inspection in a manufacturing line for semiconductor devices or the like.
SOLUTION: The manufacturing method of the semiconductor devices includes a plurality of processing operations and inspection operations. The sample inspection is included in the inspection operation and is of a step to select a given lot out of a plurality of lots and inspect the selected lot to see if a result of the processing operation is good or not. The sample inspection comprises a step of raising a flag automatically for a given lot at a constant rate to indicate that the given lot is in the subject of inspection, and a step of automatically executing a process of checking the flag when each lot is about to be subjected to the inspection operation and executing the inspection when the flag is raised for the lot while skipping the inspection when the flag is not raised.
COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2004356386A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004356386A
公开(公告)日：2004-12-16
申请号：JP2003152367
申请日：2003-05-29
申请人： Trecenti Technologies Inc , トレセンティテクノロジーズ株式会社
发明人： SASAKI YASUSHI
IPC分类号： G03F1/00 , G03F1/70 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To improve the uniformity of temperature of a semiconductor wafer upon heat treatment by preventing a conductive film from remaining in the inhibit region of the semiconductor wafer to reduce the strain of the semiconductor wafer. SOLUTION: When a positive type photoresist film R1 is formed on a polycrystalline silicon film which becomes a lower electrode E1 to transfer sequentially the pattern of a photomask onto the chip region of the semiconductor substrate 1, the transfer is applied on the inhibit region OUT of the semiconductor substrate 1. The development of the photoresist film R1 is effected while the polycrystalline silicon film is etched utilizing the remaining photoresist film R1 as a mask to form the lower electrode E1 on the chip region CA and form a pattern (dummy pattern) E1d having a configuration corresponding to the lower electrode in the chip region in the inhibit region OUT. As a result, the polycrystalline silicon film will not remain in the whole of the inhibit region OUT whereby only the strain of the semiconductor wafer (semiconductor substrate 1) is reduced and the uniformity of temperature of the semiconductor wafer upon heat treatment thereafter can be improved. COPYRIGHT: (C)2005,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式