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    • 9. 发明专利
    • Metallized structure for high electric power micro electronic device
    • 高功率微电子器件的金属结构
    • JP2010141144A
    • 2010-06-24
    • JP2008316298
    • 2008-12-11
    • Cree Incクリー, インコーポレイティッド
    • WARD ALANHENNING JASON
    • H01L21/28H01L21/338H01L29/43H01L29/47H01L29/778H01L29/78H01L29/812H01L29/872
    • PROBLEM TO BE SOLVED: To provide a metal interconnection system capable of withstanding thermal stress generated by a device of high electric power and high performance. SOLUTION: A semiconductor device structure includes: a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group-III nitrides; and an interconnect structure to the semiconductor portion, the interconnect structure including at least two diffusion barrier layers alternating with two respective high electrical conductivity layers, the diffusion barrier layers having a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions is large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供能够承受由高功率和高性能的装置产生的热应力的金属互连系统。 解决方案:半导体器件结构包括:选自由碳化硅和III族氮化物组成的组的宽带隙半导体部分; 以及与所述半导体部分的互连结构,所述互连结构包括与两个相应的高导电性层交替的至少两个扩散阻挡层,所述扩散阻挡层的热膨胀系数不同于和低于所述半导体部分的热膨胀系数 高电导率层。 相应的热膨胀系数的差异足够大以限制高电导率层的膨胀,但是小于将在相邻层之间产生超过层之间的结合强度的应变的差异。 版权所有(C)2010,JPO&INPIT
    • 10. 发明专利
    • LOW BASAL PLANE DISLOCATION BULK GROWN SiC WAFER
    • 低基本平面分离块大块碳化硅砂轮
    • JP2010006699A
    • 2010-01-14
    • JP2009154425
    • 2009-06-29
    • Cree Incクリー, インコーポレイティッド
    • POWELL ADRIANBRADY MARKTSVETKOV VALERI F
    • C30B29/36H01L21/20H01L21/338H01L29/78H01L29/812
    • C30B33/00C30B23/00C30B29/36H01L21/02378H01L21/0254H01L29/66068
    • PROBLEM TO BE SOLVED: To provide a high-quality single crystal wafer of SiC.
      SOLUTION: The wafer is an SiC wafer having a diameter of at least about 3 inches (75 mm) and at least one square inch (6.25 cm
      2 ) of continuous surface area that has a basal plane dislocation volume density of less than about 500 cm
      -2 for a 4° off-axis wafer. The production method of the wafer includes a step of forming an SiC boule having a diameter of a little larger than 3 inches, a step of slicing the boule at an angle between about 2° and 12° to 0001 plane into a wafer, wherein the wafer has a surface area including at least one square inch of continuous surface area that has a basal plane dislocation volume density of less than about 500 cm
      -2 . The high quality SiC semiconductor precursor wafer 4 produced by the above method additionally has at least one layer of at least one group III nitride layer 6.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供SiC的高品质单晶晶片。 解决方案:晶片是直径为至少约3英寸(75mm)和至少1平方英寸(6.25cm 2 SPF)的连续表面积的SiC晶片,其具有基底 对于4°离轴晶片,平面位错体积密度小于约500cm -2 。 晶片的制造方法包括形成直径略大于3英寸的SiC棒的步骤,将晶片以约2°〜12°的角度切割成0001平面的步骤切割成晶片,其中, 晶片具有包括至少一平方英寸的连续表面积的表面积,其具有小于约500cm 2的基面位错体积密度。 通过上述方法制造的高质量SiC半导体前体晶片4另外具有至少一层至少一层III族氮化物层6.版权所有(C)2010,JPO&INPIT