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81. 发明专利

JP2009157887A Method and system for controlling load store queue 审中-公开
标题翻译：用于控制加载存储队列的方法和系统
公开(公告)号：JP2009157887A
公开(公告)日：2009-07-16
申请号：JP2007338861
申请日：2007-12-28
申请人： Nec Corp , 日本電気株式会社
发明人： KOBAYASHI KOJI
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F13/1668 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To efficiently issue a request to a main storage part by reducing the activation execution times of RAS concerning a load store queue to be mounted between a cache and the main storage part. SOLUTION: A load store queue control method is the control method for holding a request to be issued to the main storage part. When the address of the first request and the address of the second request in the load store queue are the addresses included in the same processing unit in the main storage part, the method performs control to issue the first request to the main storage part together with the second request when the first request is issued to the main storage part. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过减少要安装在高速缓存和主存储部分之间的加载存储队列的RAS的激活执行时间，有效地向主存储部分发出请求。解决方案：加载存储队列控制方法是用于保存要发给主存储部分的请求的控制方法。当第一请求的地址和加载存储队列中的第二请求的地址是主存储部分中包含在相同处理单元中的地址时，该方法执行控制以向主存储部分发出第一请求以及当向主存储部分发出第一请求时的第二请求。版权所有（C）2009，JPO＆INPIT

82. 发明专利

JP2008102706A Memory control circuit 有权
标题翻译：存储器控制电路
公开(公告)号：JP2008102706A
公开(公告)日：2008-05-01
申请号：JP2006284142
申请日：2006-10-18
申请人： Canon Inc , キヤノン株式会社
发明人： MURAYAMA KOHEI , SUZUKI TAKESHI
IPC分类号： G06F12/00 , G06F13/16 , G11C11/401 , G11C11/407
CPC分类号： G11C29/02 , G06F13/1668 , G11C5/04 , G11C5/063 , G11C7/1051 , G11C29/025 , G11C29/028 , G11C29/50008 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To solve the problem that when an ODT is switched only from the aspect of signal quality, the unnecessary switching of the ODT is increased, and the power consumption of a memory device is increased as a result. SOLUTION: This memory control circuit for connecting a plurality of memory devices having an On-Die termination mechanism is provided with: ODT control registers 104 and 105 for storing ODT control information showing whether to validate or invalidate the mechanism corresponding to the memory device as the object of access among the plurality of memory devices corresponding to each of the plurality of memory devices; and an ODT control circuit 112 for controlling the ODT mechanism of each of the plurality of memory devices based on the ODT control information corresponding to the memory as the object of access of the plurality of memory devices. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了解决ODT仅从信号质量方面进行切换的问题，ODT的不必要的切换增加，结果存储装置的功耗增加。解决方案：用于连接具有片上终端机构的多个存储器件的存储器控制电路设置有：用于存储ODT控制信息的ODT控制寄存器104和105，该ODT控制信息表示是否验证或者使与存储器对应的机制无效设备作为与多个存储设备中的每一个对应的多个存储设备之间的访问对象; 以及ODT控制电路112，用于基于与作为多个存储器件的访问对象的存储器相对应的ODT控制信息来控制多个存储器件中的每一个的ODT机制。版权所有（C）2008，JPO＆INPIT

83. 发明专利

JP2008046989A Memory control device 有权
标题翻译：存储控制装置
公开(公告)号：JP2008046989A
公开(公告)日：2008-02-28
申请号：JP2006223567
申请日：2006-08-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAKAKU KAZUYA , HONDA IKUSHI , SUZUKI KENJI
IPC分类号： G06F12/06 , G06F12/00 , G11C5/00 , G11C11/403
CPC分类号： G06F13/1668
摘要： PROBLEM TO BE SOLVED: To provide a technique for increasing the number of ranks of a memory module by a small change in configuration. SOLUTION: A memory control device which accesses the memory module having a plurality of ranks includes: an interface part having a select signal line for a select signal for rank selection and an address signal line for an address signal indicating an address on a selected rank; and a control part which transmits the signal for rank selection through a part of an address signal line and the select signal line. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过配置的小的改变来增加存储器模块的等级的技术。解决方案：访问具有多个等级的存储器模块的存储器控制装置包括：具有用于等级选择的选择信号的选择信号线的接口部分和用于指示地址信号的地址信号的地址信号线选择等级以及控制部，其通过地址信号线和选择信号线的一部分发送用于等级选择的信号。版权所有（C）2008，JPO＆INPIT

84. 发明专利

JP2008021394A Memory controller 有权
标题翻译：内存控制器
公开(公告)号：JP2008021394A
公开(公告)日：2008-01-31
申请号：JP2006194804
申请日：2006-07-14
申请人： Toshiba Corp , Toshiba Lsi System Support Kk , 東芝エルエスアイシステムサポート株式会社 , 株式会社東芝
发明人： SUKEGAWA HIROSHI , NAKANO TAKESHI
IPC分类号： G11C16/02 , G11C11/22 , G11C16/04 , G11C29/04
CPC分类号： G06F13/1668 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C2211/5641
摘要： PROBLEM TO BE SOLVED: To provide a memory controller improving reliability of a system. SOLUTION: The memory controller 12 for writing data into a first semiconductor memory 11 including a plurality of memory cells MT connected with current paths in series and furnished with an electric charge accumulating layer, is equipped with: a host interface 21 for receiving first data from a host device 2; a second semiconductor memory 25 for temporarily holding second data; and an arithmetic processor 22 for producing the second data in accordance with the status of the first semiconductor memory 11 to make the second semiconductor memory 25 hold them temporarily and for writing the first data and second data into the first semiconductor memory 11. In writing the second data, the arithmetic processor 22 does not select the word lines WL0, WL31 which are adjacent to the select gate lines SGD, SGS, but selects the word lines WL1 to WL30 which are not adjacent to the select gate lines SGD, SGS. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高系统可靠性的存储器控制器。解决方案：用于将数据写入包括与当前路径串联并配有电荷累积层的多个存储单元MT的第一半导体存储器11的存储器控制器12配备有主机接口21，用于接收来自主机设备2的第一数据; 用于临时保持第二数据的第二半导体存储器25; 以及用于根据第一半导体存储器11的状态产生第二数据以使第二半导体存储器25暂时保持第二数据并将第一数据和第二数据写入第一半导体存储器11的算术处理器22.在写入第二数据，算术处理器22不选择与选择栅极线SGD，SGS相邻的字线WL0，WL31，而是选择与选择栅极线SGD，SGS不相邻的字线WL1至WL30。版权所有（C）2008，JPO＆INPIT

85. 发明专利

JP2007172129A Nonvolatile memory access control device and nonvolatile memory control system 审中-公开
标题翻译：非易失性存储器访问控制设备和非易失性存储器控制系统
公开(公告)号：JP2007172129A
公开(公告)日：2007-07-05
申请号：JP2005366432
申请日：2005-12-20
申请人： Sony Corp , ソニー株式会社
发明人： HASHIMOTO TAKUYA , MIURA KUNIHIRO , NAKAMURA TOSHINORI , NOMURA EIRYO , SATORI KENICHI , NAKANISHI KENICHI , ADACHI NAOHIRO , KONNO TAMAKI
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1668 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory access control device and a nonvolatile memory control system, in which increase in processing frequency of a processor can be suppressed to prevent retard of access operation to a nonvolatile memory, and power consumption can be thus reduced.
SOLUTION: This system comprises the nonvolatile memory 13, the CPU (processor) 11 which requests access to the memory 13, and the nonvolatile memory access control device 14 for controlling access operations including a plurality of cycles to the memory 13 according to the request of the CPU 11. The control device 14 can set information related to a series of nonvolatile memory access operations of the plurality of cycles, and includes a nonvolatile memory access operation control part 141 for controlling, upon receipt of the access request to the memory 13 from the CPU 11, the series of access operations to the memory 13 based on the set information.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：为了提供一种非易失性存储器访问控制装置和非易失性存储器控制系统，其中可以抑制处理器的处理频率的增加以防止对非易失性存储器的访问操作的延迟，并且功耗可以因此减少。解决方案：该系统包括非易失性存储器13，请求访问存储器13的CPU（处理器）11和用于根据根据本发明的存储器13控制包括多个周期的存取操作的非易失性存储器访问控制装置14 CPU11的请求。控制装置14可以设置与多个周期的一系列非易失性存储器访问操作相关的信息，并且包括非易失性存储器访问操作控制部分141，用于在接收到对来自CPU 11的存储器13，基于所设置的信息将一系列对存储器13的访问操作。版权所有（C）2007，JPO＆INPIT

86. 发明专利

JP2006155387A Computer system 审中-公开
标题翻译：电脑系统
公开(公告)号：JP2006155387A
公开(公告)日：2006-06-15
申请号：JP2004347312
申请日：2004-11-30
申请人： Yamaha Corp , ヤマハ株式会社
发明人： OKAMOTO KAZUKI , SUZUKI TOMOHIRO
IPC分类号： G06F13/36 , G06F12/06 , G06F13/16
CPC分类号： G06F13/4234 , G06F13/1668
摘要： PROBLEM TO BE SOLVED: To provide a technique that prevents data read from a bus, to which a memory is connected and from a peripheral device from colliding with each other, even if the peripheral device is connected to the bus.
SOLUTION: This computer system includes a memory a peripheral device 300, to which an address overlapping with part of an address space allocated to the memory is allocated; a CPU 200 which when accessing either the memory or the peripheral device, sends a signal matching the address of the accessed memory or device; and a bus for connecting the CPU 200 to the peripheral device 300. A switch is provided for connecting or disconnecting the CPU 200 to or from the memory via the bus. Further, the peripheral device is provided with an interface part 310, that receives the signal sent from the CPU 200 to the bus and specifies the address represented by the signal, and a decoding part 330 that turns off the switch 410, when the address specified by the interface part 310 is the address of the peripheral device.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使外围设备连接到总线，提供一种防止从存储器连接的总线和外围设备的数据读取相互冲突的技术。解决方案：该计算机系统包括外围设备300的存储器，分配与分配给存储器的地址空间的一部分重叠的地址; CPU 200，当访问存储器或外围设备时，发送与所访问的存储器或设备的地址匹配的信号; 以及用于将CPU 200连接到外围设备300的总线。提供用于经由总线将CPU 200连接到存储器或从存储器断开CPU的开关。此外，外围设备设置有接口部分310，其接收从CPU 200发送到总线的信号并指定由该信号表示的地址，以及解码部分330，其在指定的地址时关闭开关410 通过接口部分310是外围设备的地址。版权所有（C）2006，JPO＆NCIPI

88. 发明专利

JP2006107710A Integrated circuit memory device, by which existence of program error due to power failure is detectable, and its method 审中-公开
标题翻译：集成电路存储器件，由于电源故障引起的程序错误可能被检测到，并且它的方法
公开(公告)号：JP2006107710A
公开(公告)日：2006-04-20
申请号：JP2005276471
申请日：2005-09-22
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HYUN-MO , PARK CHAN-IK
IPC分类号： G11C16/02 , G01R31/28 , G06F12/16 , G11C16/06
CPC分类号： G06F13/1668 , G06F11/1004
摘要： PROBLEM TO BE SOLVED: To provide a method and a device which is capable of discriminating by a nonvolatile memory device whether a power failure is generated or not in the process of the data recording operation. SOLUTION: The integrated circuit device that supports an error detection, includes a nonvolatile memory device having a memory array therein containing a plurality of pages of memory cells, and it is demonstrated. A memory controller is also provided. The memory controller is electrically coupled to the nonvolatile memory device and configured to provide the nonvolatile memory device with a plurality of segments of page data during a page write operation. The plurality of segments of page data include checksum data constituted of a plurality of segments that designate a number of nonvolatile memory cells to be programmed with write data during the page write operation. Additional checksum data are also generated for comparison and error detection during a page read operation. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种方法和装置，其能够在非易失性存储装置中识别在数据记录操作的过程中是否产生电源故障。解决方案：支持错误检测的集成电路器件包括其中包含多页存储器单元的存储器阵列的非易失性存储器件，并且被证明。还提供存储器控制器。存储器控制器电耦合到非易失性存储器件并且被配置为在页写入操作期间向非易失性存储器件提供多个页面数据段。页面数据的多个段包括校验和数据，该校验和数据由多个片段组成，多个片段在页写入操作期间指定要用写入数据编程的非易失性存储器单元的数量。还会生成额外的校验和数据，以便在页面读取操作期间进行比较和错误检测。版权所有（C）2006，JPO＆NCIPI

89. 发明专利

JP3735377B2 Computer system 失效
公开(公告)号：JP3735377B2
公开(公告)日：2006-01-18
申请号：JP51447998
申请日：1996-09-20
申请人：株式会社日立製作所
发明人：浩光前田 , 忠幸榊原 , 輝雄田中
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08 , G06F13/16
CPC分类号： G06F13/1668

90. 发明专利

JP3631209B2 Flash that to match the latency in the read processing 有权
公开(公告)号：JP3631209B2
公开(公告)日：2005-03-23
申请号：JP2001573488
申请日：2001-03-30
申请人：マイクロンテクノロジーインコーポレイテッドMicron Technology, Inc.
发明人：ルーパーバー、フランキー、エフ．
IPC分类号： G11C16/02 , G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C8/18 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C7/106 , G06F13/1615 , G06F13/1668 , G06F13/1694 , G06F13/4243 , G11C7/10 , G11C7/1015 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/18 , G11C16/10 , G11C16/26 , G11C2207/105 , G11C2207/2281 , G11C2207/229 , G11C2216/22
摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

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