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81. 发明专利

JPS6123247A Error report system 失效
标题翻译：错误报告系统
公开(公告)号：JPS6123247A
公开(公告)日：1986-01-31
申请号：JP14358784
申请日：1984-07-11
申请人： Nec Corp
发明人： TAKAGI HAJIME
IPC分类号： G06F11/22 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To prevent severe effect even in case a subprocessor has stalled by performing the initialization to a processor having a fault and the start of a microprogram routine for report of fault through a diagnosis processor. CONSTITUTION:A microprogram routine for diagnosis discriminates at a microprogram execution control part 41 that the program run of a certain input/output controller 3 has a fault. Then a diagnosis processor 4 delivers a hardware initialization command to the controller 3 and sets an initialization state. Then the processor 4 decides the result of the diagnosis routine to judge a workable state and issues a command to a diagnosis bus control part 33 to start the microprogram routine for report of a fault. The controller 3 reports the generation of the fault to an arithmetic processor via a system bus control part 32. Thus the arithmetic processor can recognize the faulty controller 3.
摘要翻译：目的：为了防止在通过对具有故障的处理器进行初始化以及通过诊断处理器报告故障的微程序例程的启动而使子处理器停止的情况下发生严重的影响。构成：用于诊断的微程序程序在微程序执行控制部分41鉴别某个输入/输出控制器3的程序运行有故障。然后诊断处理器4将硬件初始化命令传送到控制器3并设置初始化状态。然后，处理器4决定诊断程序的结果以判断可工作状态，并向诊断总线控制部分33发出命令，以启动用于报告故障的微程序。控制器3经由系统总线控制部分32向算术处理器报告故障的产生。因此，算术处理器可以识别故障控制器3。

82. 发明专利

JPS60214052A Error reporting system 失效
标题翻译：错误报告系统
公开(公告)号：JPS60214052A
公开(公告)日：1985-10-26
申请号：JP7036884
申请日：1984-04-09
申请人： Fujitsu Ltd
发明人： MORIYOSHI SHIYUUHEI
IPC分类号： G06F9/22 , G06F11/00 , G06F11/07 , G06F11/30
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To report an important trouble speedily and properly by reporting an important error of a microprocessor itself to a host device even in case of its occurrence and recovering the microprocessor with a recovery indication from the host device. CONSTITUTION:When an MPU5 is in operation under microprogram control, a a microprogram detects an important error relating to logical contradiction in a microprogram and then executes a microprogram stop instruction in the microprogram. When the microprogram stop instruction is executed, the microprogram interrupts the operation and the MPU5 outputs an error stop signal to an OR circuit 7 at the same time; and the signal is ORed with the output of an error detecting circuit 4 and the result is outputted to an error reporting circuit 6. The error signal is transmitted to the host device 1 and an instruction indication of selective resetting is sent to a controller 2.
摘要翻译：目的：通过向主机设备报告微处理器本身的重要错误，即使发生故障并通过主机设备恢复指示恢复微处理器，即可快速正确地报告重要故障。构成：当MPU5在微程序控制下运行时，微程序检测与微程序逻辑矛盾有关的重要错误，然后在微程序中执行微程序停止指令。当执行微程序停止指令时，微程序中断操作，MPU5同时向OR电路7输出错误停止信号; 并且该信号与错误检测电路4的输出进行“或”运算，并将结果输出到错误报告电路6.该错误信号被发送到主机1，而选择性复位的指令指示被发送到控制器2。

83. 发明专利

JPS60209848A Picture forming device 失效
标题翻译：图像形成装置
公开(公告)号：JPS60209848A
公开(公告)日：1985-10-22
申请号：JP6649784
申请日：1984-04-03
申请人： Konishiroku Photo Ind Co Ltd
发明人： FUNABASHI SOUKICHI
IPC分类号： G03G21/00 , G03G21/14 , G05B23/02 , G06F11/00 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/00 , G06F11/0703
摘要： PURPOSE:To grasp accurately the operation mode at the time, when program runaway occurs, to clear up easily causes of program runaway by storing the operation mode then. CONSTITUTION:A CPU1 continues to transmit runaway detection clear pulses to a runaway detecting circuit 6 in the normal state. If this clear pulse signal is broken, runaway of the CPU1 is detected, and a reset signal is transmitted immediately to the CPU1, and a runaway detection signal is outputted for a certain period. When the CPU1 is reset, an initial routine is executed; and if the runaway detection signal is outputted then, the copy mode just before runaway is written in a storage area of a RAM5. Meanwhile, the runaway detecting circuit 6 clears the runaway detection signal when several runaway detection clear pulses are inputted thereafter.
摘要翻译：目的：准确掌握当程序发生跳闸时的操作模式，通过存储操作模式轻松清除程序失控原因。构成：在正常状态下，CPU1继续将失控检测清除脉冲发送到失控检测电路6。如果该清除脉冲信号被破坏，则检测到CPU1的失控，并且将复位信号立即发送到CPU1，并且在一段时间内输出失控检测信号。当CPU1复位时，执行初始程序; 并且如果输出失控检测信号，则在失控之前的复制模式被写入到RAM5的存储区域中。同时，当其后输入若干失控检测清除脉冲时，失控检测电路6清除失控检测信号。

84. 发明专利

JPS60195649A Error reporting system of microprogram-controlled type data processor 失效
标题翻译：微控制型数据处理器的错误报告系统
公开(公告)号：JPS60195649A
公开(公告)日：1985-10-04
申请号：JP5043884
申请日：1984-03-16
申请人： Nec Corp
发明人： TAKAGI HAJIME
IPC分类号： G06F9/22 , G06F11/07 , G06F11/22
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To prevent an entire system from being seriously affected by faults, by causing a diagnostic processor to make the error report of faults occurring in a sub-processor through a common system bus in the place of the sub-processor. CONSTITUTION:A program routine running in a diagnostic processor (SVP)4 recognizes that an abnormal condition occurs in a specific input-output controlling device (IOP)3 from the microprogram run abnormal bit of the content of a status register in the IOP3. The SVP4 edits the error status from the content of the status register and reprots the error status to an arithmetic processor (EPU)1 through a system bus 100 in the place of the IOP3. Therefore, the software of the EPU1 can receive the fault reprot, can recognize the IOP3 in which the fault occurs, and can processed the software sequence by forcedly terminating the I/O instruction.
摘要翻译：目的：为了防止整个系统受到故障的严重影响，通过使诊断处理器通过公共系统总线来代替子处理器，在子处理器中发生故障的错误报告。构成：在诊断处理器（SVP）4中运行的程序例程从IOP3中的状态寄存器的内容的微程序运行异常位识别特定输入输出控制装置（IOP）3中发生异常情况。 SVP4从状态寄存器的内容中编辑错误状态，并通过系统总线100代替IOP3将错误状态重新发送到算术处理器（EPU）1。因此，EPU1的软件可以接收到故障，可以识别发生故障的IOP3，并通过强制终止I / O指令来处理软件序列。

85. 发明专利

JPS60195647A Information processor 失效
标题翻译：信息处理器
公开(公告)号：JPS60195647A
公开(公告)日：1985-10-04
申请号：JP4913984
申请日：1984-03-16
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： FUJIMOTO KATSUHIRO
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/0703
摘要： PURPOSE:To process an error with a simple circuit, by sending prescibed information for starting a program which causes a CPU to make a prescribed error processing operation to a data bus when an operation error occurs. CONSTITUTION:When an error detecting signal R becomes high in level, the output signal of a NAND gate circuit G1 becomes high in level and the output of an output circuit OB becomes high in impedance. Accordingly, high-level/low- level signals passing through pull-up/pull-down resistances R0-R7 appear in an external bus BUS. When a memory board RAM is accessed with the signals, a CPU receives a specified instruction language formed by the resistances R0-R7. The instruction language acts as a jump instruction which jumps the operation to a program which performs a fixed error process operation and the CPU can immediately shift its operation to the execution of the error processing operation.
摘要翻译：目的：使用简单电路处理错误，通过发送预定义的信息来启动程序，当程序发生操作错误时，CPU会对数据总线进行规定的错误处理操作。构成：当误差检测信号R变为高电平时，NAND门电路G1的输出信号变为高电平，输出电路OB的输出阻抗变高。因此，通过上拉/下拉电阻R0-R7的高电平/低电平信号出现在外部总线BUS中。当使用信号访问存储器板RAM时，CPU接收由电阻R0-R7形成的指定指令语言。指令语言作为跳转指令，将操作跳转到执行固定的错误处理操作的程序，并且CPU可以立即将其操作转移到执行错误处理操作。

86. 发明专利

JPS59208664A External storage control device of data processor 失效
标题翻译：数据处理器的外部存储控制设备
公开(公告)号：JPS59208664A
公开(公告)日：1984-11-27
申请号：JP8352783
申请日：1983-05-12
申请人： Nec Corp
发明人： KAWAGUCHI TOORU
IPC分类号： G06F3/06 , G06F11/07 , G06F11/14 , G06F13/00 , G11B20/18
CPC分类号： G06F11/0721 , G06F11/0703 , G06F11/14
摘要： PURPOSE:To obtain an external storage device executing the recovery processing of an error by controlling a lower rank device by an instruction from a higher rank device to write/read out data, and after reading out the error, changing a clock period and executing retrial. CONSTITUTION:When the higher rank device 1 sends a data instruction, an interface circuit 2 sends the instruction to a write/read decoding circuit 3A. The circuit 3A analyzes the sent contents, and if the contents are data writing, sets up a device control circuit 4 to WRITE and sends the data to a device 5. In case of reading, the circuit 3A sets up the circuit 4 to READ, sends the data from the device 5 to the circuit 2 and executes error checking. If an error exists, the circuit 4 sends an error informing signal to the device 1 and the device 1 sends a clock period changing instruction to a clock period changing instruction decoding circuit 3B. The circuit 3B judges the instruction and an incremental direction indicating circuit 6 selects a reducing direction indicating circuit 7, which applies an instruction to change the clock period. The device 1 instructs retrial and the retrial is repeated until no error is checked again.
摘要翻译：目的：通过控制较低等级的设备，通过高级设备的指令来读取/读出数据，获取执行错误恢复处理的外部存储设备，读出错误后，更改时钟周期并执行重试。构成：当高级装置1发送数据指令时，接口电路2将该指令发送到写/读解码电路3A。电路3A分析发送的内容，如果内容是数据写入，则将设备控制电路4设置为写入并将数据发送到设备5.在读取的情况下，电路3A将电路4设置为读取，将数据从设备5发送到电路2，并执行错误检查。如果存在错误，则电路4向设备1发送错误通知信号，并且设备1向时钟周期改变指令解码电路3B发送时钟周期改变指令。电路3B判断指令，增量方向指示电路6选择应用指令改变时钟周期的减法指示电路7。设备1指示重试，并重复重试，直到再次检查错误。

87. 发明专利

JPS59208656A Simulator 失效
标题翻译：模拟器
公开(公告)号：JPS59208656A
公开(公告)日：1984-11-27
申请号：JP8393483
申请日：1983-05-12
申请人： Omron Tateisi Electronics Co
发明人： TANAKA TOSHIFUMI
IPC分类号： G06F11/26 , G06F11/07
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To analyze a tested result after completing the test of a device to be tested by storing information transmitted/received between a processing means and the device to be tested in a memory and outputting the stored contents. CONSTITUTION:The device 1 to be tested is connected to a processing circuit through connection devices PIA1, PIA2. A timer 3, an RAM4, an ROM5, an input device 6, a display device 7, etc. are connected to the circuit 2. A test program loaded from a floppy disc is stored in the RAM2 under control by a control program OS and test data which are the executed result of the test program are stored in the RAM4. In this case, a different display corresponding to the existence of an input/output is executed every testing times and the tested result can be analyzed after the completion of the test of the device 1 to be tested by reading the display.
摘要翻译：目的：通过将处理装置和待测试装置之间发送/接收的信息存储在存储器中并输出存储的内容，来完成待测试装置的测试，以分析测试结果。构成：被测试装置1通过连接装置PIA1，PIA2连接到处理电路。定时器3，RAM4，ROM5，输入装置6，显示装置7等连接到电路2.从软盘加载的测试程序由控制程序OS和作为测试程序的执行结果的测试数据被存储在RAM4中。在这种情况下，每测试一次执行与存在输入/输出相对应的不同显示，并且可以在通过读取显示来完成要测试的设备1的测试之后分析测试结果。

88. 发明专利

JPS59206951A Diagnostic system of circuit for detecting control storage error 失效
标题翻译：用于检测控制存储错误的电路诊断系统
公开(公告)号：JPS59206951A
公开(公告)日：1984-11-22
申请号：JP8195683
申请日：1983-05-11
申请人： Mitsubishi Electric Corp
发明人： FUJIOKA ISAO
IPC分类号： G06F11/08 , G06F11/07 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2215 , G06F11/0703 , G06F11/0727
摘要： PURPOSE:To perform highly reliable diagnoses with an inexpensive device, by storing previously a diagnostic pattern in a part of an empty area of a control storage section and performing a diagnosis by branching the execution of a control program to the diagnostic pattern at the time of diagnosis. CONSTITUTION:When an error detecting circuit (PC) 4 is diagnosed, a diagnostic pattern for supplying wrong readout information to the PC4 and generating a control storage error, is previously stored in a part of an empty area of a control storage section (CS) 1. At the time of normal operation, operations are made in accordance with control program information 2 read out from the CS1, but, when the PC4 is diagnosed, parity information 3 is branched as a next execution controlling program step. As a result, a wrong pattern read out from the CS1 is supplied to the PC4 and a control storage error occurs, and then, the error is detected by an FF5. In this way, a highly reliable diagnosis can be performed with an inexpensive device.
摘要翻译：目的：使用便宜的设备进行高度可靠的诊断，通过先前将诊断模式存储在控制存储部分的空白区域的一部分中，并通过将控制程序的执行分支到诊断模式来执行诊断，诊断。构成：当诊断出错误检测电路（PC）4时，将预先向PC4提供错误读出信息并产生控制存储错误的诊断模式预先存储在控制存储部分（CS）的空白区域的一部分中，在正常操作时，根据从CS1读出的控制程序信息2进行操作，但是当诊断出PC4时，奇偶信息3被分支为下一个执行控制程序步骤。结果，从CS1读出的错误模式被提供给PC4，发生控制存储错误，然后由FF5检测到错误。以这种方式，可以用廉价的装置执行高度可靠的诊断。

89. 发明专利

JPS59206950A Power control system 失效
标题翻译：电源控制系统
公开(公告)号：JPS59206950A
公开(公告)日：1984-11-22
申请号：JP8209383
申请日：1983-05-11
申请人： Nec Corp
发明人： TOOYA HIROKAZU , KIDO SUSUMU , UCHIDA KATSUMI
IPC分类号： H02J1/00 , G06F1/28 , G06F11/00 , G06F11/07 , G06F11/34 , H02J13/00
CPC分类号： G06F11/34 , G06F11/0703
摘要： PURPOSE:To rationalize the maintenance work of the power source section of information processing system, such as CPU, main storage device, input-output control section, peripheral device, etc., by collecting, processing, and displaying the operating condition of the power source section containing trouble data at a real time. CONSTITUTION:A power source section 6 supplies prescribed DC power to a service processor 2 and information processing devices 5-1-5-3. A system power control section 4 collects and processes prescribed operating condition data containing prescribed supervisory items related to the power source section 6 required for controlling the section 6 through a power controlling data processing means 3 composed of a control processing device 1 and service processor 2, and stores the operating condition data in the storage section of the service processor 2. Moreover, the service processor 2 outputs operating condition data related to the supervisory items as power control display data and displays the data on a CRT, etc. Therefore, data of the power source section 6 are collected and processed at a real time and, as a result, the maintenance work of the power source section can be rationalized.
摘要翻译：目的：通过收集，处理和显示电源的运行状况，使CPU，主存储设备，输入输出控制部分，外围设备等信息处理系统的电源部分的维护工作合理化源部分实时包含故障数据。构成：电源部分6向服务处理器2和信息处理设备5-1-5-3提供规定的直流电力。系统功率控制部分4通过由控制处理设备1和服务处理器2组成的功率控制数据处理装置3收集和处理包含与控制部分6所需的电源部分6有关的规定的监控项目的规定的操作条件数据，并将操作条件数据存储在服务处理器2的存储部分中。此外，服务处理器2输出与监控项目相关的操作条件数据作为功率控制显示数据，并将数据显示在CRT等上。因此，数据电源部分6被实时收集和处理，结果使电源部分的维护工作合理化。

90. 发明专利

JPS59200359A State hysteresis memory system 失效
标题翻译：状态滞后记忆系统
公开(公告)号：JPS59200359A
公开(公告)日：1984-11-13
申请号：JP7448783
申请日：1983-04-27
申请人： Nec Corp
发明人： NAGASAWA TOSHIKATSU
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To always obtain the sufficient fault analysis data by selecting an effective series of data among the fault analysis data stored in a tracer. CONSTITUTION:When the operation of a CPU is stopped due to a fault, etc., a service processor (SVP) starts the tracer reset routine. When the resetting is through with a tracer 1, the CPU gives an end report to the SVP. The SVP applies the start of execution in response to said end report. A microprogram stored in a control memory 5 is executed during execution of the CPU. A control memory access address 70 obtained at that time point and a V-bit 20 are written successively to the tracer 1 at and after the head address. If the stop conditions of a fault, etc. are detected during execution of the CPU, the CPU discontinues the program execution and gives the report of discontinuation and a tracer access address 30 set during discontinuation of program execution to the SVP. In this case, the all memory contents of the tracer 1 are delivered to the SVP in the form of the logout data 10.
摘要翻译：目的：通过在跟踪器中存储的故障分析数据中选择有效的数据系列来始终获得足够的故障分析数据。构成：当CPU由于故障等而停止运行时，服务处理器（SVP）启动示踪复位程序。当通过示踪器1复位时，CPU向SVP发送结束报告。高级副总裁应对最终报告的执行开始。在执行CPU期间执行存储在控制存储器5中的微程序。在该时间点和V位20获得的控制存储器访问地址70在头地址之前和之后连续写入示踪器1。如果在执行CPU期间检测到故障等的停止条件，则CPU停止程序执行，并且在中断程序执行期间将停止报告和跟踪访问地址30设置为SVP。在这种情况下，跟踪器1的所有存储器内容以注销数据10的形式传送到SVP。

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