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81. 发明专利

JPH02141029A AD CONVERSION CIRCUIT 失效
公开(公告)号：JPH02141029A
公开(公告)日：1990-05-30
申请号：JP29434088
申请日：1988-11-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIMURA KUNIHARU , IWATA ATSUSHI
IPC分类号： H03M1/60
摘要： PURPOSE:To convert an analog signal into a digital signal by delaying the pulse signal output having a frequency in accordance with the voltage with plural successively cascade connected delaying circuits, counting respectively and successively and adding the values. CONSTITUTION:A pulse signal P from a voltage-frequency converting circuit 2 is successively counted for respective periods of a sampling signal S1' having a frequency Nfs1 from a sampling signal input terminal 4' and a counting output CN is inserted to a delaying device 3 composed of delaying circuits D1 to DN and an FIR type digital filter 20 composed of coefficient circuits H1 to HN and an adder circuit 5. Next, it is supplied through a thinning circuit 13 with a sampling signal S1 from a sampling signal input terminal 4 to a decimation filter 12. In such a way, an analog signal can be converted into a digital signal including only a low quantizing noise.

82. 发明专利

JPH01217273A METHOD FOR TESTING INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01217273A
公开(公告)日：1989-08-30
申请号：JP4213988
申请日：1988-02-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAGATSUMA TADAO , SANO EIICHI , SHIBATA ZUIDOU , IWATA ATSUSHI
IPC分类号： G01R31/26 , G01R19/00 , G01R31/28 , G01R31/302 , H01L21/66
摘要： PURPOSE:To measure the arbitrary node in a circuit to be tested with good reproducibility, by forming an electro-optical crystal on a substrate and connecting an integrated circuit chip to be tested to a solder bump in opposed relation thereto and irradiating the same with laser beam from the rear of a chip carrier. CONSTITUTION:A membrane electro-optical crystal 2 having a reflecting film 7 applied to the surface thereof is formed on a transparent substrate 4 composed of a transparent material, and metal wirings 3 are further arranged around the electro-optical crystal of the substrate 4 for form a chip carrier 5. An integrated circuit chip 1 to be tested is further connected by a solder bump 6 in opposed relation to the electro-optical crystal 2 to attain to enhance measuring sensitivity. Further, by irradiating the electro-optical crystal 2 with laser beam from the rear of the chip carrier 5, the electrolytic value of the arbitrary node in the integrated circuit to be tested can be measured. By this method, the signal of the arbitrary node of the integreated circuit can be measured with high sensitivity, high time resolving power and good reproducibility without exerting effect on circuit operation.

83. 发明专利

JPH0116060B2 失效
公开(公告)号：JPH0116060B2
公开(公告)日：1989-03-22
申请号：JP12723980
申请日：1980-09-16
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AKAZAWA YUKIO , MATSUTANI YASUYUKI , IWATA ATSUSHI
IPC分类号： H03M1/74 , H03M1/00 , H03M1/10 , H03M1/68

84. 发明专利

JPS6230451B2 失效
公开(公告)号：JPS6230451B2
公开(公告)日：1987-07-02
申请号：JP3227781
申请日：1981-03-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MORYA TAKEHIRO , AKAZAWA YUKIO , IWATA ATSUSHI
IPC分类号： G06F7/50 , G06F7/507

85. 发明专利

JPS6039926A DIGITAL-ANALOG CONVERTER 失效
公开(公告)号：JPS6039926A
公开(公告)日：1985-03-02
申请号：JP14865883
申请日：1983-08-12
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIMURA KUNIHARU , IWATA ATSUSHI , KOBAYASHI TSUTOMU
IPC分类号： H03M1/66
摘要： PURPOSE:To obtain an analog output with high S/N by forming a signal quantized by a resolution smaller than that of an input signal into a differentiated value having a further smaller resolution by a digital differentiating device, D/A-converting the result and integrating it. CONSTITUTION:An input digital signal is subjected to interpolation to increase the sampling frequency by a digital filter 2, an n1-bit resolution is obtained and the result is fed to a differentiating modulator DELTAMOD8. A quantizer 54 of the DELTAMOD8 decreases the resolution of the input signal to n2 bits, and the signal is inputted to a local D/A converter 4 having a further smaller resolution (n3 bits) as a differentiated value of the said resolution by a digital differentiation device comprising a delay register 55 and a subtractor 56. The converter 4 converts the inputted differentiation value to an analog signal, which is integrated by an integration device 9 and the result is outputted via an analog filter 5. In this case, the relation of n1>n2>n3 is selected so as to satisfy Equation (A), where fIN is a band upper limit frequency of the input signal, fS is a smapling frequency and the input signal is an N-notation digital value.

86. 发明专利

JPS6039924A ANALOG-DIGITAL CONVERTER 失效
公开(公告)号：JPS6039924A
公开(公告)日：1985-03-02
申请号：JP14801283
申请日：1983-08-15
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIMURA KUNIHARU , IWATA ATSUSHI , KOBAYASHI TSUTOMU
IPC分类号： H03M1/12 , H03M3/04
摘要： PURPOSE:To obtain a high S/N with a low quantized accuracy by forming a quantized output into a tri-state level and spreading a DC converted error with a pulse signal so as to change over the full scale of a D/A converting circuit depending on the magnitude of the input signal level. CONSTITUTION:An input analog signal is added to an output from a pulse generator 10 at an adder 2, subtracted with a velue D/A-converting (6) an output of a quantizer Q4 sampling signals in a frequency higher than an input frequency, and the result is inputted to an integration device 3. An integrated output signal is quantized into three levels, a reference voltage VREF1 or over, a middle value between VREF1 and VREF2, and the VREF2 or below by two voltage comparators 12A, 12B of a quantizer 4 and outputted to a digital filter DF7 and the D/A converter 6. The DF7 eliminates a pulse signal spreading a DC converting error from the generator 10 and outputs a digital signal corresponding to the input analog signal. The output signal is detected by a signal amplitude detecting circuit 11 and the full scale of the D/A and the DF7 is changed over into two stages depending on the magnitude of the signal amplitude so as to improve the S/N ratio to a low input level signal.

87. 发明专利

JPS5899836A ENCODER CIRCUIT 失效
公开(公告)号：JPS5899836A
公开(公告)日：1983-06-14
申请号：JP19892681
申请日：1981-12-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUZUKI YOSHITAKE , YAMAUCHI HIROKI , IWATA ATSUSHI
IPC分类号： G06F7/00 , G06F7/74 , H03M7/00 , H03M7/04
摘要： PURPOSE:To make a digit distribution of ANDARRAY optimum, and to execute the operation of an encoder circuit at a high speed, by using a 2-input AND gate and a multi-input AND circuit, in an ANDARRAY circuit of the encoder circuit. CONSTITUTION:Binary data of N digits (N>1) is divided into plural data, which become (n) pieces of partial data S1-S3, and whether at least one of ''0'' and ''1'' is contained in the data S1 or not is detected by 2-input AND gates 11-19, and its signal is made to the upper most or the least significant input data of the lower or upper part in order. Partial data from this most or least significant bit is monitored by a multi-input AND circuit 26, and while ''1'' and ''0'' of the bit value are continued, ''1'' ane ''0'' are outputted. Relation of this output and the data S2 is taken by 2-input AND gates 20-23, and relation of an output of a multi-input AND circuit 27, and the data S3 is taken by 2-input AND gates 24, 25. Subsequently, exclusive ''or'' of the gates is taken by an EXCLUSIVE OR ARRAY circuit 2, and the binary data is outputted from a 16-4 bit binary converter 3.

88. 发明专利

JPS56126311A SWITCHED CAPACITOR CIRCUIT 失效
公开(公告)号：JPS56126311A
公开(公告)日：1981-10-03
申请号：JP3015280
申请日：1980-03-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KIKUCHI HIROYUKI , IWATA ATSUSHI , UCHIMURA KUNIHARU
IPC分类号： H03H19/00
摘要： PURPOSE:To obtain an output of integration that is free from a stray capacity, by providing a switch which performs a control with the fist phase clock plus a switch which performs a control with the second phase clock centering on the sampling capacitor. CONSTITUTION:The analog switches 33 and 34 which work with the first phase complementary clock phi1 plus the switches 31 and 32 which work with the second phase complementary clock phi2 having a different phase due to the polarity of the output to be obtained are distributed centering on the sampling capacitor 14. As shown in the input clock time chart, both of the clocks phi1 and phi2 are set at the same high or low level with the necessary switch turned on. Thus the output phase has the opposite polarity; while the clocks phi1 and phi2 are set the opposite level of the high or low level with the switch turned on to obtain the same polarity for the output signal. In such way, an integral output signal can be obtained with no effect of a stray capacity in both cases mentioned above.

89. 发明专利

JPS56126303A DYNAMIC ANALOG AMPLIFIER 失效
公开(公告)号：JPS56126303A
公开(公告)日：1981-10-03
申请号：JP2913080
申请日：1980-03-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIMURA KUNIHARU , IWATA ATSUSHI
IPC分类号： H03F3/45 , H03F3/04
摘要： PURPOSE:To increase a range of the output voltage, by connecting a current Miller circuit whose input current is the charge/discharge current of the capacity of a current control circuit in series to a low electric power amplifier using the capacity for its load. CONSTITUTION:A current Miller circuit consisting of MOSFETs 15 and 16 is connected in series to a low electric power amplifier using the capacity comprising MOSFETs 9-12 for the load in order to supply the working current. The input current of the current Miller circuit is used for the change or discharge current of the capacitor 8 of the current control circuit 17. The current is controlled by the input signal applied to the terminal 20 in such dynamic amplifier. The output current waveform between the terminals 18 and 19 and the output voltage waveform of the signal output terminal 5 are shown in the figure. The output signal is set so as to complete a setting within the time t1-t2. In such way, a small- sized capacitor 8 is obtained with a low level of voltage at the connection point 13 plus a wide range of the output voltage.

90. 发明专利

JPS56119520A PRIMARY LOWWPASS FILTER 失效
公开(公告)号：JPS56119520A
公开(公告)日：1981-09-19
申请号：JP2296780
申请日：1980-02-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： IWATA ATSUSHI , KANEKO TAKAO , UCHIMURA KUNIHARU , KIKUCHI HIROYUKI
IPC分类号： H03H11/04 , H03H11/12 , H03L7/093
摘要： PURPOSE:To obtain a circuit suitable for IC, by constituting the primary low-pass filter with the circuit which supplies a current to the capacity element by the input signal, the circuit which absorbs the current from the capacity element, and the circuit which supplies a voltage to the capacity element. CONSTITUTION:Current supply circuit H1 and current absorbing circuit H2 are connected to terminal a1 of capacity circuit 21. Circuit H1 is controlled by input signal S1 to supply current I1 to element 21. Circuit H2 absorbs current I2 from element 21 by the control of the second signal S2 having the polarity opposite to signal S1. Voltage generating circuit G is connected to the other terminal a2 of element 21. Circuit G generates voltage V1 by signal S1 and generates voltage V2 of the opposite polarity by signal S2 and supplies them to element 21 through terminal a2 and outputs output signal SO from terminal TO. Signals S1 and S2 are given at different times; and if absolute values of currents I1 and I2 and voltages V1 and V2 are made equal to each other respectively, the capacity of element 21 is small, and it is constituted with an integrated circuit.

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