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81. 发明专利

JPS6219106B2 失效
公开(公告)号：JPS6219106B2
公开(公告)日：1987-04-27
申请号：JP4035877
申请日：1977-04-11
申请人： HITACHI LTD
发明人： MINAMIBATA SHIGEAKI , FURUHATA MAKOTO
IPC分类号： H04N5/18 , H04N5/16

82. 发明专利

JPS6246484A SEMICONDUCTOR INTEGRATED CIRCUIT EQUIPMENT 失效
公开(公告)号：JPS6246484A
公开(公告)日：1987-02-28
申请号：JP18415285
申请日：1985-08-23
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO , YAMAZAKI KOICHI , WATANABE KAZUO
IPC分类号： H01L21/8229 , G11C11/34 , H01L21/8226 , H01L27/08 , H01L27/082 , H01L27/10 , H01L27/102
摘要： PURPOSE:To enhance the density of integration of a synchronizing type FF circuit by forming an integrated injection logic in the island of semiconductor having floating controlled potential and at the same time, constituting a synchronizing type FF circuit using it. CONSTITUTION:Integrated injection logic (IIL) of the first kind is portioned out to groups of G21 and G22, G41 and G42 by a master section 11 and a slave section 12. IIL of each group is formed in islands 102B, 102D of common semiconductor formed over FF circuits 1, 1, ..., and fixed to grounding potential. IIL of the second kind is portioned out to groups of G11 and G12, G31 and G32 and formed in islands 102A, 102C of common semiconductor formed over circuits 1, 1, ..., and floated from grounding potential. Thus, many synchronizing type FF circuits 1, 1, ... can be formed in islands 102A, 102B, 102C, 102D of common semiconductor.

83. 发明专利

JPS61170997A LOGICAL CIRCUIT 失效
公开(公告)号：JPS61170997A
公开(公告)日：1986-08-01
申请号：JP903685
申请日：1985-01-23
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： G11C17/08 , G11C17/00 , H03K19/091 , H03K19/177
摘要： PURPOSE:To attain an IIL logical circuit, especially large scale logical circuit integration using a ROM as a major component especially without increasing a large power consumption by connecting only a part selected among parts dividing the IIL logical circuit into plural numbers to a common ground poten tial and using an injection current source of each split IIL part in common. CONSTITUTION:Out put lines of selection signals G1-G16 are shared to each internal common potential of plural ROMs M1-M16, connected and the entire circuit other than the selected ROM is floated from a common ground potential GND and in inactivated state. On the other hand, any ROM selected by the selection signals G1-G16 is released from the floating state by connecting the internal ground potential to the common ground potential GND and only the selected ROM is supplied with the operating current (Iing) from a power supply Vcc substantially and activated. Thus, only the operating current (Iing) flowing to one ROM flows always to 16 ROM M1-16.

84. 发明专利

JPS61137422A Digital output interface circuit 失效
标题翻译：数字输出接口电路
公开(公告)号：JPS61137422A
公开(公告)日：1986-06-25
申请号：JP25915384
申请日：1984-12-10
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO
IPC分类号： H03K19/091 , H03K19/018
摘要： PURPOSE: To obtain the output interface circuit of a digital circuit which uses no high resistance and has small flowing-in current capacity of an output terminal even with relatively low resistance by shunting a current from a power source by a current mirror circuit which has a large mirror ratio, and supplying a current which is shunt to a circuit side with a small current shunt ratio to the output terminal of the digital circuit.
CONSTITUTION: The current mirror 3 which shunts the current I
0 from the power source VCC is provided and the ratio (R2=R1/n) of resistances R1 and R2 is so set that the mirror ratio (n) is large. The current I1 which is shunt to the circuit side with a small shunt ratio, i.e. resistance R1 is supplied to the output terminal of the IIL as a load current, and a current I2 which is shunt to the circuit side with the large shunt ratio, i.e. resistance R2 is DC- biased to the earth potential. When the mirror ratio (n) is set to 9, the load current I1 flowing to the output terminal of the IIL is reduced to one-tenth as large as the total current I
0 flowing through a resistance R
0 .
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了获得即使具有相对较低的电阻也不会产生高电阻的数字电路的输出接口电路，并且由电流镜电路分流来自电源的电流，该电流镜电路具有大的镜面比，并且以与电流分流的电流相对于数字电路的输出端子提供小的电流分流比的电流。构成：提供从电源VCC分流电流I0的电流镜3，并且电阻R1和R2的比（R2 = R1 / n）被设定为镜面比（n）大。以小分流比分流到电路侧的电流I1，即电阻R1作为负载电流提供给IIL的输出端，以及以大的分流比分流到电路侧的电流I2，即电阻R2被DC偏置到地电位。当镜面比（n）设定为9时，流入IIL的输出端的负载电流I1降低到流过电阻R0的总电流I0的十分之一。

85. 发明专利

JPS61125072A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：JPS61125072A
公开(公告)日：1986-06-12
申请号：JP24591784
申请日：1984-11-22
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： FURUHATA MAKOTO , OGURA SADAO , SAGA RYOHEI
IPC分类号： H01L21/8229 , G11C11/41 , H01L27/10 , H01L27/102
CPC分类号： H01L27/1025
摘要： PURPOSE:To ensure the simple reading of memory information, by providing a bipolar transistor, which is formed in the island of an electrically independent semiconductor with respect to a memory cell, between the memory cell and bit lines. CONSTITUTION:When a word line W is selected, an injection current, which is supplied to a memory cell M, is increased. When bit lines B1 and B2 are selected, only the memory cell M, in which the injection current Ic is increased, takes a current from the selected bit line B1 or B2 by a large amount. Thus the memory cell M at intersections of the word line W and the bit lines B1 and B2 is selected. The change in current corresponding to the memory information ('1' and '0') of the selected memory cell M complementarily appears on the selected bit lines B1 and B2. The current change is detected by a sense amplifier. Thus, the memory information in the selected memory cell can be read out. In this way, the reading of the memory information in the selected memory cell can be performed simply and positively.
摘要翻译：目的：为了确保对存储器信息的简单读取，通过在存储单元和位线之间提供相对于存储单元在电独立半导体的岛上形成的双极晶体管。构成：当选择字线W时，提供给存储单元M的注入电流增加。当选择位线B1和B2时，只有其中注入电流Ic增加的存储单元M从所选位线B1或B2中获取大量的电流。因此，选择字线W与位线B1和B2的交点处的存储单元M. 对应于所选存储单元M的存储器信息（'1'和'0'）的电流变化互补地出现在所选位线B1和B2上。电流变化由感测放大器检测。因此，可以读出所选存储单元中的存储器信息。以这种方式，可以简单而积极地执行所选存储单元中的存储器信息的读取。

86. 发明专利

JPS619020A Analog-digital converting circuit 失效
标题翻译：模拟数字转换电路
公开(公告)号：JPS619020A
公开(公告)日：1986-01-16
申请号：JP12933284
申请日：1984-06-25
申请人： Hitachi Ltd
发明人： KONDOU SHIZUO , HOUYA KAZUO , FURUHATA MAKOTO
IPC分类号： H03M1/36
摘要： PURPOSE: To simplify the titled device and to attain ease of operation by inputting an analog signal in common to a control terminal of plural switching elements having different threshold level and extracting the conductive state of each switching element as a 1-bit binary digital signal respectively in parallel.
CONSTITUTION: A PNP and an NPN bipolar transistor (TR) Q
11 , Q
12 are used two kinds of switching elements and an analog signal Vi is inputted in common to the two TRs Q
11 , Q
12 . Then the conductive state of the one TRQ
11 is extracted from the emitter via an inverter L1 as a binary digital signal of H (high level) and L (low level). Further, the conductive state of the other TRQ
12 is extracted from the collector via an inverter L2 as the H and L digital signal. Thus, the analog signal voltage Vi is converted into a digital signal output Dout of A, B two-bit parallel type.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了简化标题设备并通过将模拟信号共同地输入到具有不同阈值电平的多个开关元件的控制端子并且将每个开关元件的导通状态分别提取为1位二进制数字信号来简化标准设备并实现易于操作在平行下。构成：使用PNP和NPN双极晶体管（TR）Q11，Q12两种开关元件，并且将模拟信号Vi公共地输入到两个TRs Q11，Q12。然后通过反相器L1从发射极提取一个TRQ11的导通状态作为H（高电平）和L（低电平）的二进制数字信号。此外，另一个TRQ12的导通状态通过反相器L2从集电极提取为H和L数字信号。因此，模拟信号电压Vi被转换为A，B两位并行类型的数字信号输出Dout。

87. 发明专利

JPS6041485B2 失效
公开(公告)号：JPS6041485B2
公开(公告)日：1985-09-17
申请号：JP14651076
申请日：1976-12-08
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO , OOSAWA MICHINAO
IPC分类号： H03L7/18 , H03D7/00 , H03K3/72 , H03K5/00

88. 发明专利

JPS60177724A LOGIC CIRCUIT 失效
公开(公告)号：JPS60177724A
公开(公告)日：1985-09-11
申请号：JP3235884
申请日：1984-02-24
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO , OGURA SADAO , KONDOU SHIZUO , MINAMIMURA EIJI
IPC分类号： G11C17/00 , H03K19/00 , H03K19/091
摘要： PURPOSE:To increase the scale of a digital memory circuit of a logic circuit consisting of an IIL, ROM, etc. without increasing the power consumption nor increasing extremely the capacity of a drive buffer, by providing plural units of an ROM consisting of an IIL and using the input and output terminals of each ROM in common to each other. CONSTITUTION:Lower bit trains D4-D7 of logical inputs D0-D7 of 8 bits are divided into positive and negative logics by an inverter IV and then supplied in common to ROM parts M1-M16. While upper bit trains D0-D3 are divided by the inverter IV and then supplied to a selection ROM part Mo to be decoded. In other words, it is enough to supply a working current io just to either one of ROM parts. Thus it is possible to form an ROM which works on the inputs D0- D7 of an 8-bit train.

89. 发明专利

JPS59191970A Picture receiver 失效
标题翻译：图片接收器
公开(公告)号：JPS59191970A
公开(公告)日：1984-10-31
申请号：JP23422583
申请日：1983-12-14
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO , NUNOKAWA YASUHIRO , MAMETA JIYUNICHI
IPC分类号： H04N5/93 , H04N5/08
CPC分类号： H04N5/08
摘要： PURPOSE:To stabilize the vertical synchronizing pulse by resetting a counter circuit which obtains a vertical deflecting signal with a signal approximately synchronous with an additional pulse of a special reproduction mode in a production mode of said pulse and resetting the counter circuit in its initial state in other cases. CONSTITUTION:In a high-speed reproduction mode, an output signal f''v is obtained from a voltage comparator 43 when the voltage signal f'v obtained by integrating a reproduction signal fp is smaller than the reference voltage V2. While an output signal PC of an H level is obtained from a voltage comparator 45 when the output voltage Vi of an integration circuit 44 is set at a low level. Then a switch S1 is closed. In this case, a high-level output signal VRP of a voltage comparator 42 is supplied to a 1/525 counter 36 via the switch S1. Therefore the counter 36 is assuredly reset once by the signal VRP every time an additional pulse V''P appears. As a result, a vertical sawtooth current fvs is obtained from a vertical drive circuit 39.
摘要翻译：目的：为了稳定垂直同步脉冲，通过复位在所述脉冲的产生模式中以与特殊再现模式的附加脉冲大致同步的信号获得垂直偏转信号的计数器电路，并将计数器电路在其初始状态下复位其他情况。构成：在高速再现模式中，当通过对再现信号fp积分获得的电压信号f'v小于参考电压V2时，从电压比较器43获得输出信号f''v。当积分电路44的输出电压Vi被设定为低电平时，从电压比较器45获得H电平的输出信号PC。然后开关S1闭合。在这种情况下，电压比较器42的高电平输出信号VRP经由开关S1提供给1/525计数器36。因此，每当出现附加脉冲V''P时，计数器36被确定地由信号VRP复位一次。结果，从垂直驱动电路39获得垂直锯齿电流fvs。

90. 发明专利

JPS5932227A Buffer circuit using mos transistor 失效
标题翻译：使用MOS晶体管的缓冲电路
公开(公告)号：JPS5932227A
公开(公告)日：1984-02-21
申请号：JP14110582
申请日：1982-08-16
申请人： Hitachi Ltd
发明人： KOBORI YASUNORI , OKAMOTO CHIKAYUKI , FUKUSHIMA ISAO , NISHIJIMA HIDEO , KUWABARA KAZUMI , FURUHATA MAKOTO
IPC分类号： H03K19/08 , H03K19/0175 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H03K19/09448
摘要： PURPOSE:To reduce the transmission distortion of an alternating signal, by making a drain current of an MOS transistor(TR) pair equal, and further making a drain-source voltage equal so as to transmit accurately the DC level independently of an input signal level. CONSTITUTION:A drain current of the MOS TR1 and an emitter current of a TR6, and a drain current of an MOSTR2 and an emitter current of a TR7 are equal respectively, and these current values are denoted respectively I1 and I2. An output voltage VOUT is equal to the sum of an input voltage VIN, a gatesource voltage VGS1 of the TR1, and a base-emitter voltage VBE6 of the TR6 subtracted by a base-emitter voltage VBE7 of the TR7 and a gate-source voltage VSG2 of the TR2. A current value I6 of a current source 8 is almost equal to the I1 and the I1 is nearly equal to the I2, because of the relation of a current value 2I0 of a current source 9, 2I0=I1+I2 I0+I2. Thus, the drain-source voltage of the TRs 1, 2 is almost equal because of the relation of VBE6approx.=VBBE7, resulting that the relations of VGS1 VGS2, and VOUT VIN are obtained. Since the temperature characteristic of the TRs 1, 2 is equal, no temperature drift takes place.
摘要翻译：目的：为了减少交流信号的传输失真，通过使MOS晶体管（TR）对的漏极电流相等，并进一步使漏极 - 源极电压相等，以便与输入信号电平无关地精确地传输DC电平。构成：MOS TR1的漏极电流和TR6的发射极电流以及MOSTR2的漏极电流和TR7的发射极电流分别相等，这些电流值分别表示I1和I2。输出电压VOUT等于TR1的输入电压VIN，栅源电压VGS1和由TR7的基极 - 发射极电压VBE7减去的TR6的基极 - 发射极电压VBE6之和和栅极 - 源极电压 TR2的VSG2。由于电流源9的电流值2I0与2I0 = I1 + I2 I0 + I2的关系，电流源8的电流值I6几乎等于I1，I1几乎等于I2。因此，由于VBE6approx = VBBE7的关系，TR1,2的漏极 - 源极电压几乎相等，从而得到VGS1 VGS2和VOUT VIN的关系。由于TR1,2的温度特性相等，所以不会发生温度漂移。

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