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    • 83. 发明专利
    • PACKET PASSING CONTROL SYSTEM
    • JPH06244897A
    • 1994-09-02
    • JP2529193
    • 1993-02-15
    • FUJITSU LTDFUJITSU COMMUNICATION SYST
    • TAKAHASHI HIROSHI
    • G06F13/00H04L12/70H04L29/06H04L12/56
    • PURPOSE:To enable packet passing control to be comducted to be conducted without increasing the load of a system. CONSTITUTION:This system is provided with chase number storage part 11e for storing the chase number of a finally transmitted packet for each pair of addresses in which either a transmission source address or a destination address is made different at least, and a chase number addition part 11b adds the chase number to the packet at the time of packet reception and continues the packet to a queue corresponding to a transmission priority level. At the time of packet transmission, a queue managing part 11f decides packets to be transmitted in the order of priority levels and reception, a chase number processing part 11g calculates a chase number Ni of the finally transmitted packet among the packets provided with the same transmission source address and the same destination address as that packet from the chase number storage part 11e, when a chase number N of a packet to be transmitted is larger than the chase number Ni of the finally transmitted packet, that packet is transmitted, the contents of the chase number storage part 11e are updated with the chase number N of the packet and when the chase number is smaller, that packet is not transmitted but abandoned.
    • 86. 发明专利
    • ERROR LOG CONTROL SYSTEM
    • JPH04111025A
    • 1992-04-13
    • JP22922290
    • 1990-08-30
    • FUJITSU LTD
    • ISHIHARA KENJITAKAHASHI HIROSHI
    • G06F11/34
    • PURPOSE:To obtain the significant error log information and to curtail the number of times of write of a nonvolatile memory by collecting only error log information by a first machine check after turning on a power source of a device. CONSTITUTION:When a control means (flip-flop) 6 is turned off by turning on a power source of a device, and a first machine check is detected after turning on the power source of the device, error log information is collected and stored in a nonvolatile memory 3. Also, when the control means 6 is turned on, thereafter, even if the machine check is detected, the error log information is not collected, and the error log information is not stored in the nonvolatile memory 3. Accordingly, only the error log information by a first machine check after turning on the power source can be collected and stored. In such a way, significant error log information is obtained, and the number of times of write to the nonvolatile memory 3 to which the number of times of write is limited is curtailed.
    • 87. 发明专利
    • SLAVE EXCHANGE DATA TRANSFER SYSTEM
    • JPH03292035A
    • 1991-12-24
    • JP9440490
    • 1990-04-10
    • FUJITSU LTD
    • TAKAHASHI HIROSHITERATSU TAKAYUKI
    • H04Q3/545H04M3/00
    • PURPOSE:To start the operation of each slave exchange in the order suitable for the operation of an exchange system by designating the transfer sequence optionally when a slave exchange data is transferred simultaneously to plural slave exchanges. CONSTITUTION:A priority registration means 100 registers sets of priority p-pm corresponding to slave exchanges 21-2n. When the necessity of transferring a slave exchange data (d) respectively to the plural slave exchanges 2 takes place, a transfer destination selecting means 200 references the priority (p) registered already by the priority registration means 100 and selects a slave exchange 2 with higher priority (p) with priority as a transfer destination slave exchange of the slave exchange data (d). Thus, when the slave exchange data is transferred simultaneously to the plural slave exchanges, it is possible to designate optionally the order of transfer and the start of the operation of each slave exchange is attained in the order suitable for the operation of the exchange system and the service performance of the relevant exchange system is improved.
    • 88. 发明专利
    • INITIALIZATION SYSTEM
    • JPH02188814A
    • 1990-07-24
    • JP811489
    • 1989-01-17
    • FUJITSU LTD
    • TAKAHASHI HIROSHI
    • G06F1/24G06F12/00
    • PURPOSE:To initialize a memory and a memory circuit without using any exclusive hardware by supplying the output received from an address register storing the address of the memory to the memory circuit at initialization. CONSTITUTION:The specific data is set at a memory data register 4 and a 1st address register 2 storing the address of a memory 1 is added via an adder 3. At the same time, the entire area of the memory 1 is initialized. In such a case, the optional several bits of the register 2 are taken out and supplied to a memory circuit (internal register) 6 via a multiplexer 9. Thus the optional data supplied from an arithmetic circuit 5 is also set at the register 6. Then the register 6 is also initialized and no addition circuit is required for initialization of a 2nd address register 7 which stores the address of the register 6. Thus the hardware quantity is reduced.