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81. 发明专利

JPS57111667A DATA PROCESSING CIRCUIT 失效
公开(公告)号：JPS57111667A
公开(公告)日：1982-07-12
申请号：JP18705180
申请日：1980-12-27
申请人： FUJITSU LTD
发明人： NAKATANI SHIYOUJI , TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F7/76 , G06F17/16
摘要： PURPOSE:To transfer data, which has multiple data format like doubled-precision floating-point data and fixed-point data, through a less number of buses by using the same aligning circuit. CONSTITUTION:At the high-order digit parts and low-order digit parts of input registers IR-0-IR-3, split input section data MI-0-MI-7 are provided, and their outputs are transferred to output section data M0-1, M0-3, M0-5, and M0-7. An aligning circuit 3 requires only 32 buses for 4-byte data transfer between the section data. For 8-byte data transfer, output section data M0-0, M0-2, M0-4, and M0--6 are provided, and between those data and said input section data MI-0, MI-2, MI-4, and MI-6, 4 4-byte buses each, i.e. 16 buses in all are required. Consequently, the aligning circuit 3 manages with 52 buses for 4-byte transfer.

82. 发明专利

JPS5797170A CONTROL SYSTEM 失效
公开(公告)号：JPS5797170A
公开(公告)日：1982-06-16
申请号：JP17358880
申请日：1980-12-09
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , TAMURA HIROSHI , UCHIDA KEIICHIROU , OKAMOTO TETSUO
IPC分类号： G06F17/16 , G06F9/30
摘要： PURPOSE:To raise the processing efficiency, by detecting a working state of prescribed timing, and idle timing, and starting the next access from the idle timing. CONSTITUTION:A processing instruction is inputted to a decoder 20, and the instruction converted to a code is inputted to an insturction start controlling circuit 21. The instruction start controlling circuit 21 detects an idle timing by an idle detecting circuit 22 of a bank timing in accordance with the inputted instruction, and also detects a working state of the first ooerand by a detecting circuit 23. Moreover, the instruction is inputted to a multiplying instruction and adding instruction processing and controlling circuit 24 and 27, respectively, the timing of the banks which said circuits are using is controlled by controlling circuits 25, 28, the residual cycle number of said mutiplication and addition is controlled by controlling circuits 26, 29, and it is informed to the instruction start controlling circuit 21 that said residual cycle number is

83. 发明专利

JPS5757372A Pipeline operating device 失效
标题翻译：管道操作装置
公开(公告)号：JPS5757372A
公开(公告)日：1982-04-06
申请号：JP13196580
申请日：1980-09-22
申请人： Fujitsu Ltd
发明人： UCHIDA KEIICHIROU , OKAMOTO TETSUO , TAMURA HIROSHI , OKUYA SHIGEAKI , AZUMA ISAO
IPC分类号： G06F12/06 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053
摘要： PURPOSE:To execute the vector operation efficiently, by supplying element data of the same number in memory banks to a pipeline operating part simultaneously in a pipeline operating device. CONSTITUTION:In a pipeline operating device, elements of vector registers are interleaved and stored in memory banks 3-6 divided into plural vector registers, and element data of the same number are stored in the same memory bank. The same element data in memory banks are supplied to pipeline oprating parts 27 and 29 simultaneously and are operated. Consequently, a specific memory bank is not occupied during vector calculation. Since elements of the same number are set in the same memory bank, the control is facilitated.
摘要翻译：目的：通过在管道操作装置中同时向管道操作部分提供相同数量的存储体中的元件数据，从而有效地执行向量操作。构成：在流水线操作装置中，向量寄存器的元素被交织并存储在分成多个向量寄存器的存储体3-6中，并且相同数量的元素数据被存储在同一个存储体中。存储体中相同的元件数据同时被提供给管道驱动部件27和29并被操作。因此，在矢量计算期间，不占用特定的存储体。由于相同数量的元件设置在相同的存储体中，因此便于控制。

84. 发明专利

JPS5757371A Address controlling system for pipeline operating device 失效
标题翻译：用于管道操作装置的地址控制系统
公开(公告)号：JPS5757371A
公开(公告)日：1982-04-06
申请号：JP13196480
申请日：1980-09-22
申请人： Fujitsu Ltd
发明人： AZUMA ISAO , TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F17/16
CPC分类号： G06F12/0607
摘要： PURPOSE:To reduce the number of multiplexers considerably to simplify the constitution and the access control, by shifting addresses of memory banks successively to perform the access control for read and write of required elements. CONSTITUTION:In a pipeline operating device, address registers 35-38 where addresses to access memory banks 19-22 are set are connected in series. Consequently, the address set in the address register 35 can be shifted to address registers 36- 38 successively, and elements ao-an and bo-bn required for operations are read out successively from memory banks 19-22. Operation results co-cn are set to prescribed addresses of memory banks successively.
摘要翻译：目的：为了简化结构和访问控制，为了简化结构和访问控制，通过连续地移位存储体的地址来执行读和写所需要的元素的访问控制。构成：在流水线操作装置中，设置访问存储体19-22的地址的地址寄存器35-38被串联连接。因此，可以将地址寄存器35中设置的地址连续地移动到地址寄存器36-38，并且从存储体19-22连续地读出操作所需的元件ao-an和bo-bn。操作结果连续地设置为存储体的规定地址。

85. 发明专利

JPS5733479A Buffer invalidation control system 失效
标题翻译：缓冲无效控制系统
公开(公告)号：JPS5733479A
公开(公告)日：1982-02-23
申请号：JP10589080
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： ITOU MIKIO , KOGA SATOSHI , TAMURA HIROSHI
IPC分类号： G06F12/08
CPC分类号： G06F12/0806
摘要： PURPOSE:To reduce the quantity of hardware and simplify the logic, by temporarily holding the buffer invalidation address to be sent to another processor into the address pipeline register group. CONSTITUTION:A buffer invalidation BI flag is added to an address pipeline AP register group 25 by an address selecting circuit 17. The circuit 17 also selects the contents of plural registers prescribed in the group 25 based on the BI flag. A BI address sending circuit sends the address selected through the circuit 17 to a processor having a buffer memory in the form of a BI address. Then the BI address to be sent to another processor is held temporarily in the register group 25 when the writing access is given to a main memory.
摘要翻译：目的：为了减少硬件数量并简化逻辑，通过临时保存要发送到另一个处理器的缓冲区无效地址到地址管道寄存器组中。构成：地址选择电路17将地址流水线AP寄存器组25中的缓冲器无效BI标志加到地址管理AP寄存器组25中。电路17还根据BI标志选择组25中规定的多个寄存器的内容。 BI地址发送电路将通过电路17选择的地址发送到具有BI地址形式的缓冲存储器的处理器。然后，当向主存储器提供写访问时，要发送到另一处理器的BI地址被暂时保存在寄存器组25中。

86. 发明专利

JPS5731079A Vector processor 失效
标题翻译：矢量处理器
公开(公告)号：JPS5731079A
公开(公告)日：1982-02-19
申请号：JP10589880
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： NAKATANI SHIYOUJI , UCHIDA KEIICHIROU , TAMURA HIROSHI , OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8053
摘要： PURPOSE:To control access time to a vector register and to enable access control with less idle time by providing the vector register that is constituted by a plurality of bank units and is made to be an interleave structure between a main storage device and an arithmetic pipeline. CONSTITUTION:Vector registers #0VR-#nVR are corresponded so that said registers are displayed in each of bank units 1-0-1-7 and the registers #0VR- #nVR are made to be an interleave structure. Each element data from said registers are read and set in registers 4-1-4-7 and further outputs from the registers 4-0, 4-1 are inputted to an arithmetic part 5, and output from the register 4-7 is inputted to a pipeline operating part 5 and output from the register 4-7 is inputted to a memory pipeline 2. Access of the registers #0VR and #nVR through write registers 3-0-3-1 by the operating part 5 and the line 2. The access is controlled in a bank controlling part 7 and controlled by timing from the control part.
摘要翻译：目的：为了控制向量寄存器的访问时间，并通过提供由多个存储体单元构成的向量寄存器，并使其成为主存储设备和算术流水线之间的交错结构，从而使空闲时间更短的访问控制。构成：向量寄存器＃0VR-＃nVR相对应，使得所述寄存器显示在每个存储体单元1-0-1-7中，寄存器＃0VR- #nVR被做成交织结构。来自所述寄存器的每个元件数据被读取并设置在寄存器4-1-4-7中，并且来自寄存器4-0，4-1的另外的输出被输入到算术部分5，并且从寄存器4-7输出到流水线操作部分5并从寄存器4-7输出输入到存储器流水线2.操作部分5和行2通过写寄存器3-0-3-1访问寄存器＃0VR和#nVR 存取控制在银行控制部分7中，并由控制部分的定时控制。

87. 发明专利

JPS5730062A Access control system 失效
标题翻译：访问控制系统
公开(公告)号：JPS5730062A
公开(公告)日：1982-02-18
申请号：JP10462980
申请日：1980-07-30
申请人： Fujitsu Ltd
发明人： NAKATANI SHIYOUJI , TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F12/00 , G06F13/18 , G06F17/16
CPC分类号： G06F13/18
摘要： PURPOSE:To make the processing of vector data stored as scattering in a plurality of storage devices easy, by making access request of consecutive access request delayed for a certain time. CONSTITUTION:A vector processor 1, central processor 2-1, and channel device 2-2 use a high speed storage device HSS and a main storage divece MSU in time division via a storage control dovice 3. When a series of data from the vector processor 1 between the main storage device MSU and the high speed storage device HSS are accessed, if the HSS access is made immediately after the MSU access especially, and when the access requests A1, A2 are made consecutively, the access request A2' delaying the access request A2 consecutive in time t1, is formed.
摘要翻译：目的：通过使连续访问请求的访问请求延迟一定时间，使得存储在多个存储设备中的散射的矢量数据的处理变得容易。构成：矢量处理器1，中央处理器2-1和通道设备2-2经由存储控制设备3以时分方式使用高速存储设备HSS和主存储器潜水MSU。当来自矢量的一系列数据访问主存储装置MSU和高速存储装置HSS之间的处理器1，如果在MSU访问之后立即进行HSS访问，并且当连续进行访问请求A1，A2时，访问请求A2'延迟形成了时间t1连续的访问请求A2。

88. 发明专利

JPS5727363A Vector data processor 失效
标题翻译：矢量数据处理器
公开(公告)号：JPS5727363A
公开(公告)日：1982-02-13
申请号：JP10153680
申请日：1980-07-24
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI , MOGI MASANORI , OKAMOTO TETSUO , KAWAI SATORU
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8053
摘要： PURPOSE:To facilitate control by preventing access requests from colliding with each other in a bank while employing multiplebank constitution for vector registers. CONSTITUTION:Vector registers are composed of banks B0-B7. Respective elements #0, #1-#8. of the vector registers VR0, VR1-VR8 are stored in the banks B0, B1-B8. Similarly, elements are assigned to the banks, and readout vector data are synchronized by a buffer register 5, thereby inputting the element #i of the vector register VR0, and the element #i of the vector register VR1 to an operator 9 at the same time.
摘要翻译：目的：通过防止访问请求在银行中相互冲突，同时采用向量寄存器的多组织结构来促进控制。构成：矢量寄存器由银行B0-B7组成。相关元素＃0，＃1-＃8。矢量寄存器VR0，VR1-VR8存储在存储体B0，B1-B8中。类似地，将元件分配给存储体，并且读出矢量数据由缓冲寄存器5同步，从而将矢量寄存器VR0的元件#i和向量寄存器VR1的元件#i输入到操作器9 时间。

89. 发明专利

JPS5727361A Vector data processor 失效
标题翻译：矢量数据处理器
公开(公告)号：JPS5727361A
公开(公告)日：1982-02-13
申请号：JP10152980
申请日：1980-07-24
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI , UCHIDA KEIICHIROU , OKUYA SHIGEAKI , OKAMOTO TETSUO , AZUMA ISAO
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8053
摘要： PURPOSE:To attain access to a vector register efficiently by providing a means of prescribing the timing where each access requesting origin is capable of accessing each element storage area. CONSTITUTION:When an access access requesting origin ER2 makes an access request, an access request selecting circuit 58 fetches the inbank address of an address register 35 with a #1 time slot, and sends it in a register 50. When an access requesting origin ER3 makes an access request, the access request selecting circuit 58 fetches the inbank address of an address register 36 with a #2 time slot, and sets it in the register 50.
摘要翻译：目的：通过提供规定每个访问请求来源能够访问每个元素存储区域的定时的方式来有效地访问向量寄存器。构成：当请求原址ER2的访问访问进行访问请求时，访问请求选择电路58以＃1个时隙取出地址寄存器35的存储库地址，并将其发送到寄存器50.当请求原始ER3的访问进行访问请求时，访问请求选择电路58以＃2时隙取出地址寄存器36的存储库地址，并将其设置在寄存器50中。

90. 发明专利

JPS5693165A DATA PROCESS SYSTEM 失效
公开(公告)号：JPS5693165A
公开(公告)日：1981-07-28
申请号：JP16899379
申请日：1979-12-25
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： G06F12/08 , G06F13/00 , G06F15/16
摘要： PURPOSE:To reduce the sending frequency of the store address in a simple and effective way, by storing the store address having an invalidated data of a buffer memory in the address buffer memory and then inhibiting the sending of the new store address which coincides with the contents of the store address buffer memory. CONSTITUTION:When a coincidence is obtained between the new store address given from the control circuit part 12 which performs the busy check, decision of priority and others for a memory control device and the store address wherein the data of the buffer memory stored in the address buffer memory 21 etc. are invalidated, the gate circuit 27 etc. are closed via the comparators 23 etc. to inhibit the setting of the new store address to the register 13-2. While in case no coincidence is secured for the new store address, not only the circuit 27 but the gate circuit 25 are opened. Thus the address set to the register 13-2 makes the buffer memory of the CPU1 and others invalid. At the same time, the contents of the memory 21 is renewed. Accordingly, the sending frequency of the store address can be reduced effectively without affecting other factors, thus increasing the processing speed.

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