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1. 发明专利

JPH07230447A VARIABLE SPEED DATA INPUT CONTROLLER 失效
公开(公告)号：JPH07230447A
公开(公告)日：1995-08-29
申请号：JP2138294
申请日：1994-02-18
申请人： FUJITSU LTD
发明人： KAWANISHI TOSHIJI , NOMURA OSAMU , NAGASHIMA TETSUO , IINO TAKASHI , OKUYA SHIGEAKI
IPC分类号： G06F13/12 , G05B19/42 , G06F17/15
摘要： PURPOSE:To prevent the efficiency of arithmetic such as FFT arithmetic by an arithmetic processor from decreasing due to variation of the transfer speed and delay quantity of input data. CONSTITUTION:When an arithmetic processor performs the arithmetic processing such as FFT for respective data sets 105 consisting of data 104 of K successive samples, it is supposed that the number of data processed by the arithmetic processor in each unit time is N times as large as the number of data inputted by a shift register part 101 in each unit time. In this case, a data set which is shifted in segmentation start position in a data sequence by K/N samples is transferred from the shift register part 101 to a buffer register part 102 each time the arithmetic processor completes preparations for arithmetic for a new data set, and the data set is inputted to the arithmetic processor through an output data selection control part 103.

2. 发明专利

JPH06149859A DATA TOTALIZING DEVICE 失效
公开(公告)号：JPH06149859A
公开(公告)日：1994-05-31
申请号：JP29887392
申请日：1992-11-09
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , NAKAZURU TOSHIRO , KUBO SHINICHI , FUJIE SHIGEKIMI
IPC分类号： G06F17/14 , G06F15/332
摘要： PURPOSE:To provide a data totalizing device which can reduce the capacity of an input totalizing memory. CONSTITUTION:A data totalizing device contains a totalizing memory 10 which stores the result of addition obtained for each of plural input values, an addition circuit 12 which disuses the input value designated to be thinned for each simultaneous input of the prescribed number of values and the input values designated to be totalized are added to the corresponding result of addition stored in the memory 10 to store again this result of addition in the memory 10, a control memory 14 where the information showing the input value designated to be thinned and the input values designated to be totalized are individually set in regard of the simultaneous input of all values, and a control information output means 16 which outputs the corresponding information out of the memory 14 for each simultaneous input of values.

3. 发明专利

JPH0467220B2 失效
公开(公告)号：JPH0467220B2
公开(公告)日：1992-10-27
申请号：JP5003486
申请日：1986-03-07
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI
IPC分类号： G06F13/00 , G06F11/22

4. 发明专利

JPH0359461B2 失效
公开(公告)号：JPH0359461B2
公开(公告)日：1991-09-10
申请号：JP17602184
申请日：1984-08-24
申请人： FUJITSU LTD
发明人： SEKINE MAKOTO , OKUYA SHIGEAKI
IPC分类号： G06F13/10 , G06F9/46 , G06F13/12

5. 发明专利

JPH0253123A CLOCK CYCLE SETTING DEVICE 失效
公开(公告)号：JPH0253123A
公开(公告)日：1990-02-22
申请号：JP20387288
申请日：1988-08-18
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , KOYABU MASAO , NISHIDA HIDEHIKO , IYOTA HIDEO , MASUDA JITSUO
IPC分类号： G06F1/08 , G06F1/12
摘要： PURPOSE:To easily set the clock cycles among devices having different action clock cycles when data are transferred among these devices by using a means which sets the 1st and 2nd clock cycles within a fixed allowable range when a basic clock cycle is changed. CONSTITUTION:A CPU, a main storage unit MSU and a channel controller CHP work with a selected basic clock cycle Ta. While the interface adaptors IA and a channel device work with a 1st clock Tb and a 2nd clock cycle Tc respectively. In case the clock Ta is changed, the register value of an action assuring range setting circuit 2 is set so that the clocks Tb and Tc are set in a fixed action assuring range. Then an optimum Ta is set by a basic cycle setting circuit 1 when the cycles Tb and Tc are changed.

6. 发明专利

JPS6161416B2 失效
公开(公告)号：JPS6161416B2
公开(公告)日：1986-12-25
申请号：JP9169681
申请日：1981-06-15
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , OKAMOTO TETSUO , SAKAMOTO KAZUSHI
IPC分类号： G06F9/38 , G06F17/16

7. 发明专利

JPS6142308B2 失效
公开(公告)号：JPS6142308B2
公开(公告)日：1986-09-20
申请号：JP10469480
申请日：1980-07-29
申请人： FUJITSU LTD
发明人： OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F7/00 , G06F9/38 , G06F17/16

8. 发明专利

JPS6120905B2 JPS6120905B2 - 失效
公开(公告)号：JPS6120905B2
公开(公告)日：1986-05-24
申请号：JP10152980
申请日：1980-07-24
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI , UCHIDA KEIICHIRO , OKUYA SHIGEAKI , OKAMOTO TETSUO , AZUMA ISAO
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8053

9. 发明专利

JPS6191740A Memory access control system 失效
标题翻译：存储器访问控制系统
公开(公告)号：JPS6191740A
公开(公告)日：1986-05-09
申请号：JP21331384
申请日：1984-10-12
申请人： Fujitsu Ltd
发明人： EGAWA HIROYUKI , OKUYA SHIGEAKI
IPC分类号： G06F12/06 , G06F12/00
摘要： PURPOSE: To improve the throughput of access of a memory control unit by providing a memory request origin device with a bank information holding mechanism and a memory request generation control mechanism.
CONSTITUTION: A control part 15 compares a memory request taken out of a memory request queue with pieces of information held in registers 16
1 W16
n constituting a pipeline P; when there is a bank number to be accessed at a memory request among the pieces of bank information held in the registers 16
1 W16
n , a selector 17 is instructed to put the memory request in the memory requet queue 12 again, and when not, the selector 17 is commanded to send the memory request to the memory control unit.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过提供具有存储器信息保持机制和存储器请求生成控制机制的存储器请求原始设备来提高存储器控制单元的访问吞吐量。构成：控制部分15将从存储器请求队列取出的存储器请求与保存在构成流水线P的寄存器161-16n中的信息块进行比较; 当存储在存储器请求中的存储体号存储在寄存器161-16n中保存的存储区信息中时，选择器17被指示再次将存储器请求置于存储器请求队列12中，而当不存在时，命令选择器17将存储器请求发送到存储器控制单元。

10. 发明专利

JPS6160147A Processing request monitor system 失效
标题翻译：处理请求监控系统
公开(公告)号：JPS6160147A
公开(公告)日：1986-03-27
申请号：JP18199484
申请日：1984-08-31
申请人： Fujitsu Ltd
发明人： OKUYA SHIGEAKI
IPC分类号： G06F11/30 , G06F11/00 , G06F13/00
CPC分类号： G06F11/006
摘要： PURPOSE:To prevent the deterioration in the system performance after a fault is detected by allocating the spare identification numbers to each port register and then using these numbers when the processing request is discontinued after the fault is detected. CONSTITUTION:A latch 30 is set and an output signal line 40 is turned on in an abnormal state where no result information is obtained at an output register 16 for a fixed period or longer after a latch 20 is set with the signal applied to a signal line 21. When a signal line 33 which sets a port register under an idle state is turned on, a latch 41 is set with the next control clock. The processing request given by detection of the fault is discontinued when the line 40 is turned on. Then the corresponding port registers 10-0-10-3 are set under idle states respectively and can accept a new processing request. The spare identification numbers are used for the subsequent processing requests when the latch 41 is turned on.
摘要翻译：目的：为了防止在检测到故障后系统性能的恶化，将备用标识号分配给每个端口寄存器，然后在检测到故障后停止处理请求时使用这些号码。构成：在锁存器20被设置为施加到信号的信号之后，锁存器30被置位并且输出信号线40在异常状态下导通，在异常状态下，在输出寄存器16处获得固定时间段或更长时间的结果信息当将在空闲状态下设置端口寄存器的信号线33导通时，锁存器41被设定为下一个控制时钟。当线路40接通时，停止检测故障时的处理请求。然后相应的端口寄存器10-0-10-3分别设置在空闲状态，并可以接受新的处理请求。当锁存器41接通时，备用识别号码用于随后的处理请求。

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