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81. 发明专利

JPH02224040A METHOD AND DEVICE FOR LOADING DATA 失效
公开(公告)号：JPH02224040A
公开(公告)日：1990-09-06
申请号：JP25194589
申请日：1989-09-29
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAMOTO AKIRA , TSUBOI TOSHIAKI , HONMA SHIGEO , NAKAMURA KATSUNORI , KANBAYASHI KOUSAKU , KITAJIMA HIROYUKI , KURANO AKIRA , NOZAWA MASASHI
IPC分类号： G06F12/08 , G06F3/06
摘要： PURPOSE:To decrease the loading overhead by determining a record group loaded into a cache, based on an existing state in the cache, of a record in an access object track of an input/output request from a host system. CONSTITUTION:A disk controller is connected to a disk device 2 and a central processing unit 1, and also, provided with a cache memory 36 for setting a physical area on the disk device 2 as a cache management unit. In this state, when data in the cache management unit containing an area which becomes an access object from the central processing unit 1 does not exist at all in the cache memory 36, initial loading for loading only the data of the area which becomes the access object from the central processing unit 1 to the cache memory 36 is executed. Thereafter, when an access is executed to other data than the data stored in the cache memory 26 already, other data than the data stored in the cache memory 36 in this cache management unit is loaded additionally to the cache memory 36. In such a way, the loading overhead is decreased.

82. 发明专利

JPH02214213A DATA SEPARATOR FOR HDD REQUIRING NO ADJUSTMENT OF SELF-RUNNING OSCILLATION FREQUENCY 失效
公开(公告)号：JPH02214213A
公开(公告)日：1990-08-27
申请号：JP3361189
申请日：1989-02-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YOSHINO YOSHINORI , WATANABE TAKASHI , URAGAMI KEN , KOJIMA SHINICHI
IPC分类号： G11B20/10 , H03K3/282 , H03L7/099
摘要： PURPOSE:To make the PLL synchronizing characteristic constant by setting a VCO self-running oscillation frequency with high accuracy so as to make the pull-in range in positive and negative phases nearly constant at the time of forming a PLL circuit. CONSTITUTION:A VCO 1 and a programmable current source 2 are formed on one and same semiconductor substrate. Then the programmable current source is used to correct a VCO oscillation reference control current corresponding to the fluctuation of the VCO self-running oscillation frequency due to dispersion of components thereby setting the VCO self-running oscillation frequency with high accuracy. Moreover, the programmable current source 2 controls the VCO oscillation reference control current I with resistance voltage division and the resistance voltage division ratio is decided by ROM information in the programmable current source 2. Thus, the fluctuation in the VCO self- running oscillation frequency attended with dispersion in components and their temperature characteristic is suppressed and the pull-in available range at positive and negative phases is made uniform and a wide capture range and locking range at high speed transfer rate are attained.

83. 发明专利

JPH02206086A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPH02206086A
公开(公告)日：1990-08-15
申请号：JP2390289
申请日：1989-02-03
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI MICROCUMPUTER ENG
发明人： AKIBA YUTAKA , MATSUMOTO SHINZO , HAMAMOTO TATSUO , KAMIMURA YOSHIYUKI , SEKINO MITSURU , NAKADAI HIROSHI , NISHIDA HIDEKI , MITANI MASAO
IPC分类号： G11C11/14
摘要： PURPOSE:To improve the uniformity of a holding magnetic field by shifting in parallel and placing the center axes of the upper and the lower magnet plates in a bias magnetic field generation use magnetic circuit. CONSTITUTION:When a bubble chip 2 is inclined by an angle theta against a magnet plate 7, a holding magnetic field HDC is given by an expression I. An edge effect of the magnet plate is given by a second term of the expression I. At the time of approaching an end part of the magnet plate 7, an HX component increases, and also, HX is generated in the direction for negating a first term of the expression I, therefore, uniformity of the magnetic field HDC is deteriorated. Therefore, by shifting in parallel and placing the upper magnet plate and the lower magnet plate 7-1, 7-2 in the positive and the negative directions, respectively against the X axis direction, HX is not generated in the end part against the chip 2, and even if it is generated, it exists in the direction for strengthening a first term of the expression I, and the uniformity of the magnetic field HDC can be improved.

84. 发明专利

JPH02205135A FRAME CONSTITUTION DEFINING SYSTEM 失效
公开(公告)号：JPH02205135A
公开(公告)日：1990-08-15
申请号：JP2390389
申请日：1989-02-03
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA MASAYUKI , TAKAHASHI YASUHIRO , TERADA MATSUAKI
IPC分类号： H04L12/42
摘要： PURPOSE:To prohibit transmission data to be carried by generating a frame in which a control field representing the prohibition of the setting of the transmission data on a packet is set at the time of generating the frame just before generating the frame based on new constitution definition by a master node. CONSTITUTION:The master node 101 checks the constitution definition of the frame of the current frame 500 before the frame 500 based on the new constitution definition is generated. When a minipacket/TDM field 512 whose definition is changed from a minipacket 512a to a TDM area 512b exists, the master node 101 performs state transition from a minipacket transmittable/receivable state 200 to a constitution definition changing state 210, And interrupts the transmission of the minipacket. The master node 201 generates the frame 500 in which a symbol displaying the prohibition of the transmission of the minipacket different from the one of ordinary display set at the transmittable/ receivable state 200 of the frame delimiter 510 of the frame 500 at the constitution definition changing state 210.

85. 发明专利

JPH02205130A DATA TRANSFER METHOD 失效
公开(公告)号：JPH02205130A
公开(公告)日：1990-08-15
申请号：JP2390589
申请日：1989-02-03
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUNODA TOMOAKI , MIZUHARA NOBORU , YOSHIOKA SHUNICHI
IPC分类号： H04L1/14 , H04L12/02 , H04L29/14
摘要： PURPOSE:To shorten the data transfer completion time by applying comparison check with transmitted data by performing the reception of data transmitted on a channel B on one side while performing data transmission on the channel B on the other side, and performing the re-transmission of the data when detecting an error on a channel D. CONSTITUTION:Both an outgoing side terminal 11 and an incoming side terminal 12 are connected to an ISDN(Integrated Services Digital Network) 13 by a subscriber line 14. The subscriber line 14 is provided with an ISDN fundamental interface, and two B channels (for user information) and one D channel (for control information) are provided after being multiplexed. Transfer data 15 are stored in the memory devices 16 in the outgoing and incoming terminals, and blocked to fixed length and packetized, then, transmitted on the channel B. And a transfer managing table 21 is housed in the memory device to control a transfer method, and the setting/reference of it is performed by a communication control part 18.

86. 发明专利

JPH02199545A METHOD OF AUTOMATING OS OPERATION 失效
公开(公告)号：JPH02199545A
公开(公告)日：1990-08-07
申请号：JP1765089
申请日：1989-01-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MORIYAMA HIROSHI , TANAKA TOSHIHARU , YOSHIZAWA YASUFUMI , HASHIMOTO TADAO
IPC分类号： G06F11/28 , G06F9/46
摘要： PURPOSE:To make it possible to apply a command after outputting a specified message by transferring a corresponding command to a virtual computer control program based upon an operation procedure previously formed by a user at the time of transferring a message between two operating systems. CONSTITUTION:The user forms the operation procedure including a message sentence consisting of the group of a message and an operating system (OS) control command or the group of a message and a virtual machine control program(VMCP) command at first and stores the procedure in an operation procedure file 206. When the 1st OS 302 transfers a message to be outputted to a virtual console 207 to the 2nd OS 301, the OS 301 compares the received message with a message stored in the file 206, and when both the messages coincide with each other, transfers its corresponding command to a VMCP 201. Thus, the command can be applied after outputting the specified message.

87. 发明专利

JPH02195711A FILTER CIRCUIT 失效
公开(公告)号：JPH02195711A
公开(公告)日：1990-08-02
申请号：JP1397789
申请日：1989-01-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SEKIGUCHI SATOSHI , OKUBO YUICHI , YONETANI NOBUAKI
IPC分类号： H03F1/34 , H03H11/12
摘要： PURPOSE:To equivalently enlarge capacitor capacity at an input signal, and obtaining a filter circuit with a low interrupting frequency characteristic by charging/discharging a capacitor by means of a differential signal formed according to the emitter ratio of a differential transistor(TR) which converts the received output signal of an input circuit into a current signal. CONSTITUTION:An input signal Vin is received by an input circuit A1 of a filter circuit, and output voltages by means of TRs Q3 and Q4, where the collector currents of TRs Q1 and Q2 of the circuit A1 flow, are applied to the bases of TRs Q6 and Q7, and Q8 and Q9, and Q14 and Q15 which respectively constitute voltage/current converting circuits VIC1 and VIC2. The voltage conforming to the emitter area ratio of the differential TRs Q6 and Q9, and Q7 and Q8 of the circuit VIC1 is converted into the current signal, charged/discharged to/from a capacitor C1, and fed back to the circuit A1. Further the output of the circuit A1 is inputted through a load circuit by means of the differential TRs Q14 and Q15, and Q16 and Q17 to a TR Q19 of an output amplifying circuit A2, and a second output current is outputted with a reference voltage as a direct current component.

88. 发明专利

JPH02195394A DISPLAY CONTROLLER 失效
公开(公告)号：JPH02195394A
公开(公告)日：1990-08-01
申请号：JP1397589
申请日：1989-01-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SHIMIZU JUNICHI
IPC分类号： G06F3/153 , G06T15/00 , G09G5/36
摘要： PURPOSE:To perform three-dimensional plotting and the display of data plotted by means of the three-dimensional plotting without burdening a host processor and software by administering the physical space of a frame buffer corresponding to a three-dimensional logical space and converting plotted data into two-dimensional data. CONSTITUTION:A graphic display controller 1 which controls the physical space of the frame buffer 2 corresponding to the three-dimensional logical space directly plots the data processed after receiving a three-dimensional plotting command in which three-dimensional X, Y and Z values are taken as parameter on the frame buffer 2 and converts the data into the two-dimensional display data in a display controlling action to give to a display device. The display controller 1 which is regarded as a peripheral device with respect to the host processor 3 administers a three-dimensional plotting function and the two-dimensional display control of the data plotted by the three-dimensional plotting function, so that the three-dimensional plotting and the display of the data plotted by the three-dimensional plotting are performed without burdening the host processor 3 and the software.

89. 发明专利

JPH02187850A BUS ARBITRATION SYSTEM 失效
公开(公告)号：JPH02187850A
公开(公告)日：1990-07-24
申请号：JP714589
申请日：1989-01-13
申请人： HITACHI LTD , SAKAMURA TAKESHI , HITACHI MICROCUMPUTER ENG
发明人： SAKAMURA TAKESHI , NAKAGAWA TAKAAKI , TAKANO MAKOTO , MIYASHITA KOICHI
IPC分类号： G06F13/374 , G06F15/16 , G06F15/177
摘要： PURPOSE:To improve the activity ratio of a bus by deciding and storing bus use sequence successively according to priority, and performing the delivery of the right of using of a bus according to stored bus use sequence. CONSTITUTION:A microcomputer system on which a bus arbitration system is applied is constituted of plural modules. In the module A, a priority level number generation circuit BNG which realizes a bus arbitration function on a microprocessor CPU that is the center of control, a priority comparator BCP, and an arbitration control circuit ABC are provided, and it decides the bus use sequence successively according to the priority allocated to the request of the use of the bus, respectively, and stores respective bus use sequence in a bus master sequence storage circuit MRG. And by performing the delivery of the right of using of the bus among the modules according to the stored bus use sequence, the activity ratio of the bus can be improved.

90. 发明专利

JPH02176864A INQUIRY PROCESSING SYSTEM INCLUDING SUMMERIZED FUNCTION 失效
公开(公告)号：JPH02176864A
公开(公告)日：1990-07-10
申请号：JP33110688
申请日：1988-12-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATO KAZUHIRO , YAMAMOTO YOICHI , NAMIOKA MIYOKO , MOGI KEIJI
IPC分类号： G06F12/00 , G06F17/30
摘要： PURPOSE:To decrease a processing load by executing an inquiry optimizing processing with the use of summerized information by means of a summerized function inquiry optimizing part when the inquiry processing including the summerized function in a retrieve condition expression, etc., is executed. CONSTITUTION:A data base supervising system 4 accepts a data base inquiry request issued from an application program or terminals 1 and 2. A system control part 40 controls the whole system 4, and a DB processing request syntax analyzing part 41 checks the syntax of the data base inquiry request. A DB processing request meaning analyzing part 42 checks the meaning of the data base inquiry request, and a DB processing request optimizing part 43 sets the optimizing processing sequence of the data base inquiry with the use of the processing result of the analyzing part 42. A DB processing request type execution processing part 44 generates an executing code by using the processing result of the optimizing part 43, accesses the data base, and obtains the processing result of the inquiry.

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