专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明专利

JP2003332461A Method of manufacturing semiconductor element including triple well structure 有权
标题翻译：制造三元结构的半导体元件的方法
公开(公告)号：JP2003332461A
公开(公告)日：2003-11-21
申请号：JP2002379437
申请日：2002-12-27
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： OH JAE-GEUN
IPC分类号： H01L21/761 , H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0928 , H01L21/823892
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is suitable for controlling the deterioration of threshold voltage and refresh characteristic of a transistor formed on the p-well surrounded by the n-well among the triple wells.
SOLUTION: The method of manufacturing the semiconductor element comprises the steps of forming, on the surface of a semiconductor substrate, a profiled first conductivity type firs well (44) in a concentration reduced below the preset value in order to isolate the adjacent second conductivity type second wells (45, 43) and forming a profile second conductivity type second wells (45, 43) in a concentration increased above the preset value consisting of a first region (45) surrounded by the first well and a second region (43) isolated from the first region with the first well.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件适用于控制在三阱中由n阱包围的p阱上形成的晶体管的阈值电压和刷新特性的劣化。解决方案：制造半导体元件的方法包括以下步骤：在半导体衬底的表面上形成浓度降低到预设值以下的成型的第一导电类型的第一阱（44），以隔离相邻第二导电类型第二阱（45,43），并且以高于由第一阱包围的第一区域（45）和第二区域（45）组成的预定值形成分布第二导电类型第二阱（45,43） 43）与第一个井分离第一个区域。版权所有（C）2004，JPO

72. 发明专利

JP2003318113A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003318113A
公开(公告)日：2003-11-07
申请号：JP2002120623
申请日：2002-04-23
申请人： Toyota Industries Corp , 株式会社豊田自動織機
发明人： NONAKA YOSHINORI
IPC分类号： H01L21/761 , H01L21/205 , H01L21/76
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where occurrence of a defect in an epitaxial layer of a device forming region, which is caused by formation of a buried layer, can be prevented and can be easily manufactured, and its manufacturing method.
SOLUTION: An n-type buried layer is formed on a semiconductor substrate 1 in a device forming region A. In a region B adjacent to the region A, a buried region 9 for causing the defect, which consists of an n-type impurity diffusion region 7 and a p-type impurity diffusion region 8 located to contact with both sides of the n-type impurity diffusion region 7, is formed. An n-type epitaxial layer 2 is grown on both of the device forming region A and the adjacent region B. In the adjacent region B, a stress concentrates on the n-type epitaxial layer 2 grown from the interface portion between the impurity diffusion regions 7 and 8 to cause the defect 10, thereby, the excellent n-type epitaxial layer 2 in which the occurrence of defect is inhibited can be formed in the device forming region A.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种半导体器件，其可以防止并且容易地制造由形成掩埋层而引起的器件形成区域的外延层中的缺陷的发生，并且其制造方法。解决方案：在器件形成区域A中的半导体衬底1上形成n型掩埋层。在与区域A相邻的区域B中，用于引起缺陷的掩埋区域9由n- 形成与n型杂质扩散区域7的两侧接触的p型杂质扩散区域7和p型杂质扩散区域8。在器件形成区域A和相邻区域B两者上生长n型外延层2.在相邻区域B中，应力集中在从杂质扩散区域之间的界面部分生长的n型外延层2上如图7和图8所示，导致缺陷10，从而能够在器件形成区域A中形成抑制缺陷发生的优异的n型外延层2.权利要求（C）2004，JPO

73. 发明专利

JP3431517B2 失效
公开(公告)号：JP3431517B2
公开(公告)日：2003-07-28
申请号：JP29042598
申请日：1998-10-13
IPC分类号： H01L29/73 , H01L21/331 , H01L21/761 , H01L21/8222 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L29/732

74. 发明专利

JP3424667B2 失效
公开(公告)号：JP3424667B2
公开(公告)日：2003-07-07
申请号：JP2000313918
申请日：2000-10-13
IPC分类号： H01L21/761 , H01L21/205 , H01L21/304 , H01L21/306 , H01L21/324

75. 发明专利

JP2003188391A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2003188391A
公开(公告)日：2003-07-04
申请号：JP2001389655
申请日：2001-12-21
申请人： SANKEN ELECTRIC CO LTD
发明人： MATSUZAKI AKIHIKO , IWABUCHI AKIO
IPC分类号： H01L29/872 , H01L21/761 , H01L29/47 , H01L29/861 , H01L29/87
摘要： PROBLEM TO BE SOLVED: To solve the problem that the chip area of a Schottky barrier diode grows large, where the Schottky diode has a JBS structure in which PN junctions are arranged in parallel at a Schottky junction to improve a breakdown voltage. SOLUTION: A second N-type semiconductor region comprising an epitaxial layer is formed on a first N + -type semiconductor region 7. A third N + -type semiconductor region 9 is provided, where the third N + -semiconductor region has a plurality of island-like sections 9' in a sectional shape. A fourth P + - semiconductor region 10 having a small area is provided among the island-like sections 9' of the third semiconductor region 9. An anode electrode 2 is provided, where the anode electrode 2 is subjected to Schottky contact to the third semiconductor region 9, and is subjected to low-resistance contact to the fourth semiconductor region. COPYRIGHT: (C)2003,JPO

76. 发明专利

JP3400528B2 失效
公开(公告)号：JP3400528B2
公开(公告)日：2003-04-28
申请号：JP6518694
申请日：1994-04-01
IPC分类号： H01L21/76 , H01L21/74 , H01L21/761 , H01L27/08

77. 发明专利

JP2003124304A SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT, AND INSULATION ISOLATION METHOD OF SEMICONDUCTOR REGION 审中-公开
公开(公告)号：JP2003124304A
公开(公告)日：2003-04-25
申请号：JP2001311444
申请日：2001-10-09
申请人： TOYOTA CENTRAL RES & DEV
发明人： MIZUNO KENTAROU , TSUKADA ATSUSHI , FUJITSUKA TOKUO
IPC分类号： G01L9/04 , H01L21/761 , H01L29/84
摘要： PROBLEM TO BE SOLVED: To reduce a leak current in a p-n junction 218 when a p-n junction and a p-n isolation are formed for the insulation isolation of a p-type gauge resistor 216. SOLUTION: A gauge resistor peripheral part 201 has a p-type gauge resistor 216 and an n-type well 212 surrounding the p-type gauge resistor 216. Positions 216a and 212a close to each other on both sides of a p-n junction 218 of the p-type gauge resistor 216 and the n-type well 212 are fixed to high potentials and positions 216b and 212b close to each other on both the sides of the p-n junction 218 but different from the positions 216a and 212a are fixed to low potentials.

78. 发明专利

JP2003124229A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：JP2003124229A
公开(公告)日：2003-04-25
申请号：JP2001311637
申请日：2001-10-09
申请人： SONY CORP
发明人： YOKOYAMA SATOSHI
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/761 , H01L21/768 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To extend a depletion layer of an impurity diffusion layer under a gate electrode while suppressing an increase in the resistance of the impurity diffusion layer. SOLUTION: There are provided a gate electrode 12 formed via a gate oxide film 17 on a P well layer 3 defined by a field oxide film 6 for device isolation, and an N type source region 18 and drain region 19 provided on a P well layer 3 located on opposite sides of the gate electrode 12. At least the drain region 19 is provided from a position where it overlaps the gate electrode 12 to the field oxide film 6, and impurity diffusion concentration is adjusted by multiple ion doping such that the impurity diffusion concentration is lowest below the gate electrode 12, and the impurity diffusion concentration is distributed denser as it goes away from the gate electrode 12. The resistance of the impurity diffusion layer is substantially the same as in a prior art, and the N type drain region 19 where a depletion layer below the gate electrode 12 is extended can be provided on the P well layer 3.

79. 发明专利

JP3393544B2 失效
公开(公告)号：JP3393544B2
公开(公告)日：2003-04-07
申请号：JP4179997
申请日：1997-02-26
IPC分类号： H01L21/8247 , H01L21/265 , H01L21/74 , H01L21/761 , H01L27/08 , H01L27/115 , H01L29/788 , H01L29/792

80. 发明专利

JP2003037113A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003037113A
公开(公告)日：2003-02-07
申请号：JP2001221214
申请日：2001-07-23
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YAMASHITA TAISUKE , YAMAMOTO FUMIHISA , TERAJIMA TOMOHIDE
IPC分类号： H01L21/331 , H01L21/761 , H01L21/8222 , H01L27/06 , H01L27/07 , H01L29/732
CPC分类号： H01L21/761 , H01L27/0766
摘要： PROBLEM TO BE SOLVED: To provide a drive circuit whose power loss is small in a semiconduc tor device including a bipolar transistor.
SOLUTION: A bipolar transistor 78 is formed on a semiconductor substrate 122, and a Schottky diode 80 is formed in a collector region 68 of the bipolar transistor 78. Potential separation layers 66, 82 and 84 are arranged for potentially separating the collector region 68 from a semiconductor substrate 62.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种在包括双极晶体管的半导体装置中功率损耗小的驱动电路。解决方案：双极晶体管78形成在半导体衬底122上，并且肖特基二极管80形成在双极晶体管78的集电极区域68中。电势分离层66,82和84被布置用于将集电区68从半导体基板62。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式