专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明专利

JPH01280988A PICTURE SIGNAL RECORDER 失效
公开(公告)号：JPH01280988A
公开(公告)日：1989-11-13
申请号：JP11133488
申请日：1988-05-06
申请人： CANON KK
发明人： FUJIMOTO MAKOTO
IPC分类号： H04N1/64 , H04N5/77 , H04N9/79 , H04N9/797 , H04N9/80 , H04N9/81 , H04N9/896
摘要： PURPOSE:To record a video signal with high picture quality even to a color component onto a recording medium by recording the 1st and 2nd recording picture signals by one frame generated in the 1st and 2nd recording picture signal generating means to separate areas of an recording medium. CONSTITUTION:A control means 158 controlling the generation of the recording picture signal in the 1st and 2nd recording picture signal generating means is provided so that the rotation of a color difference signal in color difference line sequential signals Y1, Y2 included in part of the 2nd recording picture signal corresponding to the part of the 1st recording picture signal and in the part of the 1st recording picture signal differs from each other. Moreover, recording means 141-144 recording the 2nd recording picture signal by one frame formed by the 1st and 2nd recording picture signal generating means on separate areas on the recording medium are provided. Thus, the picture signal with high definition is recorded on the recording medium without deterioration.

72. 发明专利

JPH01264492A JITTER DETECTOR FOR VTR RECORDING AND REPRODUCING VIDEO SIGNAL 失效
公开(公告)号：JPH01264492A
公开(公告)日：1989-10-20
申请号：JP9318088
申请日：1988-04-15
申请人： SHARP KK
发明人： ISHIKAWA MASAKAZU
IPC分类号： H04N9/896 , H04N9/89
摘要： PURPOSE:To detect a reproduced jitter with high accuracy by reproducing a prescribed FM recording signal and detecting the zero crossing point of a narrow-band FM carrier with the trailing edge of a horizontal synchronizing signal as a reference. CONSTITUTION:A video signal is reproduced and demodulated by a reproducing circuit 10B, which is frequency-modulated by an FM carrier to phase-synchronize with the leading edge of a horizontal synchronizing signal recorded on a magnetic tape, and a phase continuous compensating signal to suppress an FM carrier phase fluctuation is inserted into the front port of the horizontal synchronizing signal. Further, the zero crossing point of the FM carrier, which has the minimum time base fluctuation with a high C/N by a BPF23, no offset error of a d.c. component, and a phase without continuous demodulation errors at a resetting point in the phase continuous compensating signal, is detected at a jitter detecting circuit 25 with the trailing edge having comparatively small noise of a delay horizontal synchronizing signal to pass through a delay pulse forming part 24 of a jitter detecting circuit 20 as the reference, and the reproduced jitter can be detected with high accuracy.

73. 发明专利

JPH01220995A TIME BASE CORRECTION DEVICE 失效
公开(公告)号：JPH01220995A
公开(公告)日：1989-09-04
申请号：JP4426288
申请日：1988-02-29
申请人： TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
发明人： OBATA HIROSHI , KOGA TAKASHI , YONEDA MINORU , ENOMOTO AKIHIKO , MIYAZAKI YOSHINOBU
IPC分类号： H04N9/896 , H04N9/89
摘要： PURPOSE:To enable correction with excellent linearity by applying phase locking of a drive clock pulse fed to an analog digital converter to a horizontal synchronizing signal and allowing also the burst signal to be controlled automatically at high and low frequencies at the horizontal synchronizing signal. CONSTITUTION:If there is any time base fluctuation in an analog video signal in an analog digital converter 31, the phase of the clock pulse is controlled in following thereto. Thus, a means to control the drive clock pulse is provided for the purpose. That is, the input video signal is fed to a synchronizing separator circuit 35, which separates the horizontal synchronizing signal HD to supply it to a phase comparator 36. Moreover, in order to extract a burst signal, a burst timing signal is generated and fed to a burst gate circuit 41. Thus, the time base fluctuation is compensated from a low over a high frequency with high accuracy and the effect of the temperature characteristic or the like is not affected because of digital processing, high reliability is obtained and the linearity of the compensation characteristic is improved.

74. 发明专利

JPH01215193A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH01215193A
公开(公告)日：1989-08-29
申请号：JP3997288
申请日：1988-02-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SEKIMOTO KUNIO , MORIMOTO TAKESHI
IPC分类号： H04N9/79 , H04N9/89 , H04N9/896
摘要： PURPOSE:To prevent right/left shift of pattern by comparing a color frame of an input composite video signal and a color frame of an output composite video signal so as to control the storage time of a video signal. CONSTITUTION:When an output of a frequency divider 38 is inverted and a delay device 39 is counted from a 3rd field of an input video signal, the output video signal of the field becomes the 3rd field and coincident with the color frame of the input video signal. Since the number o lines of a 2 fields is 525, the phase of the output of the frequency divider 40 and the vertical synchronizing signal of the input video signal is inverted in the 1st and 3rd fields of the input video signal. Thus, the delay time from the input video signal till the reset signal of vertical frequency division by pulse switching is changed by one line and the timing of the input video signal of the vertical readout signal to the vertical synchronizing signal is changed by one line and the storage time of the time base correction device(TBC) is changed by one line. Thus, the color frame of the input/output composite video signal is made coincident.

75. 发明专利

JPH01108896A SEQUENTIAL SCANNING CONVERTING TELEVISION RECEIVER 失效
公开(公告)号：JPH01108896A
公开(公告)日：1989-04-26
申请号：JP26370187
申请日：1987-10-21
申请人： NIPPON DENKI HOME ELECTRONICS
发明人： OKADA YUKIHIRO
IPC分类号： H04N9/896 , H04N9/89 , H04N11/22
摘要： PURPOSE:To obtain high picture quality without jitters to also a non-standard video signal by processing the writing of a time axis correcting memory and digital processing before that by a clock phase-locking a horizontal synchronizing signal. CONSTITUTION:A time axis correcting part 4 lies between a Y/C demodulating part 3 and a scanning lines number converting part 5, the writing/reading clocks of a time axis correcting memory 4A are made independent, the former is made into a clock phase-locking the horizontal synchronizing signal, the latter is made into a clock phase-locking a color sub-carrier and the clocks of the pre-stage and the post-stage of the time axis correcting part 4 are respectively fitted to these clocks. Consequently, in the processing to the writing of the time axis correcting memory 4A, the jitters in the non-standard NTSC signal itself and the jitters due to the digital processing are dissolved and processing after the reading of the time axis correcting memory can be processed by the clock phase-locking the color sub-carrier without the jitters. Thus, an R, a G and a B signals of high picture quality can be obtained.

76. 发明专利

JPS6450692A RECORDING DEVICE AND REPRODUCING DEVICE 失效
公开(公告)号：JPS6450692A
公开(公告)日：1989-02-27
申请号：JP20781387
申请日：1987-08-20
申请人： CANON KK
发明人： SAKATA TSUGUHIDE
IPC分类号： H04N9/79 , H04N9/86 , H04N9/89 , H04N9/896
摘要： PURPOSE:To fix a moire pattern generated on a monitor screen at the time of reproduction by correcting signals equivalent to the synchronizing signal part of luminance signals which are angle-modulated and to the pedestaral part of chrominance components by means of two specified reference frequency signals. CONSTITUTION:The luminance signals which have passed through an FM modulator 8 are supplied to a change over switch 16 and a phase comparator 10. The clock signals of 381 fH, whose phase is synchronized with that of the frequency fH of horizontal synchronizing signals in a PLL circuit 46 are generated from horizontal synchronizing signals which have been separated in a horizontal synchronizing signal separation circuit 44 through a composite synchronizing signal separation circuit 22, and the sync chip part frequency of the having FM modulated luminance signals is fixed to 381 fH by the PLL loop of the FM modulator 8 the phase comparator 10 a disconnection switch 12 a loop filter 14 the FM modulator 8. On the other hand, the clock signals of 381 fH, which are converted into 381 fH/5 in a frequencydivider 48 are supplied to a phase comparator 66, and the signal frequency in a blanking period prior to the R-Y signals of color difference line sequential signals which are modulated in an FM modulator 64 is fixed to 381 fH/5. Consequently, respective FM modulation signals hold a constant phase relation, whereby moire is not conspicuous.

77. 发明专利

JPS63313987A METHOD FOR REDUCING NUMBER OF MOVTION VECTOR OF DIGITAL TELEVISION IMAGE REDUCTION METHOD 失效
公开(公告)号：JPS63313987A
公开(公告)日：1988-12-22
申请号：JP14235288
申请日：1988-06-09
申请人： SONY CORP
发明人： KURAIBU HENRII GIRAADO , BUINSENTO KAARU HARADAIN
IPC分类号： H04N11/00 , H04N7/01 , H04N7/173 , H04N7/26 , H04N7/32 , H04N7/36 , H04N7/46 , H04N9/877 , H04N9/896 , H04N11/04 , H04N11/20 , H04N11/24
摘要： PURPOSE:To prevent an image from out-of-focused and to decrease judder by constituting a vector reducer with a register to receive an input, a motion vector field memory, and a processor to select a suitable motion vector. CONSTITUTION:The vector reducer 40 is composed of eight pieces of registers R101-108, four pieces of motion vector field memories 109-112, a processor 113, and an output memory 114. The memories 109-112 operate periodically; during a time when the following field data in the following field is being written in a fourth memory, the remaining three memories supply data for the current field, the following field, and the preceeding field. At consecutive fields, the data is in the current field and the preceeding field which is prepared for being finally re-written. In order to determine the best four out of seven motion vectors, the processor 113 selects the four whose fidelity indices (FOM) are minimum out of total seven motion vectors.

78. 发明专利

JPS63313980A EVALUATION METHOD FOR MOVING VECTOR OF TELEVISION PICTURE 失效
公开(公告)号：JPS63313980A
公开(公告)日：1988-12-22
申请号：JP14235388
申请日：1988-06-09
申请人： SONY CORP
发明人： BUINSENTO KAARU HARADAIN , KURAIBU HENRII GIRAADO
IPC分类号： H04N11/00 , H04N7/01 , H04N7/26 , H04N7/32 , H04N7/46 , H04N9/877 , H04N9/896 , H04N11/20 , H04N11/24
摘要： PURPOSE:To upgrade resolution in an output field and to obtain a moving image with least obscurity by determining the movings of an image at points apants from each other for lengths equal to a prescribed numbers of picture elements in the horizontal and vertical directions by block matching method to obtain a moving vector, and determining sub-picture element offset representing the moving in such a field of image data as not equal to the cipher-times of the interval between said picture elements. CONSTITUTION:The moving of a television picture at the points distant from each other for the lengths equal to the prescribed numbers of picture elements in the horizontal and vertical directions are determined by block matching method to obtain a moving vector, and a discrimination for selecting a moving vector is provided by determining sub-picture element offset representing the moving in such a field of picture data not equal to the integer- times of the interval between said picture elements. Respective sub-picture element offsets are determined correlatively with the moving in the horizontal and vertical directions. In the block matching method, the minimum differences at just three positions that are a point in the center of the block, a point shifted to the left by 16-sample length, and a point shifted to the right by also 16-sample length are tested. The method is started from these points, subsequently, the minimum differences among the nine pieces of positions disposed symmetrically around these stating points are tested with less prescribed number of samples or lines for a step.

79. 发明专利

JPS6364958B2 失效
公开(公告)号：JPS6364958B2
公开(公告)日：1988-12-14
申请号：JP12918179
申请日：1979-10-05
IPC分类号： H04N5/95 , G11B5/588 , G11B20/02 , H04N5/937 , H04N5/956 , H04N9/877 , H04N9/896

80. 发明专利

JPS63286090A METHOD FOR SYNCHRONIZATION LOCKING OF PLL CIRCUIT 失效
公开(公告)号：JPS63286090A
公开(公告)日：1988-11-22
申请号：JP12183987
申请日：1987-05-19
申请人： PIONEER ELECTRONIC CORP
发明人： MORIYAMA YOSHIAKI
IPC分类号： H04N9/896 , H03L7/08 , H03L7/087 , H04N9/89
摘要： PURPOSE:To contrive to swift and stably synchronize locking to a color burst signal by resetting the phase of a signal of a chrominance carrier frequency so as to minimize the initial phase error between a signal of the chrominance carrier frequency and a color burst signal in switching an object of PLL locking from the reproduced horizontal synchronizing signal into the color burst signal. CONSTITUTION:Suppose that a range of +180 deg.--180 deg. of a phase error thetaobtained by a phase comparator 27 is expressed in terms of the complement of 2 as 011,...1 to 100,...0, then a PLL control circuit 20 decides the mode of reset based on the value of the high-order 3-bit. For example, the phase error thetais in the range of +45 deg.--45 deg. in figure (a), and the phase of the clock fSC is reset so that the position S4 is to be a position Sl. Thus, the phase error thetais decreased in the range of 0-45 deg. as shown in figure (b). Since the initial phase error theta of the color burst signal in the changeover is within + or -45 deg., the locking to the color burst signal is attained stably at a high speed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式