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71. 发明专利

JPH07121443A INFORMATION PROCESS SYSTEM AND ITS OPERATING METHOD 失效
公开(公告)号：JPH07121443A
公开(公告)日：1995-05-12
申请号：JP20317294
申请日：1994-08-29
申请人： IBM
发明人： KAHLE JAMES ALLAN
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
摘要： PURPOSE: To make a prefetch instruction valid by inputting 2nd information from a prefetch memory to a cache memory when 1st information includes the 2nd information and inputting the 2nd information from a system memory in the other case. CONSTITUTION: When target data information is not stored in a cache memory 12, a processor 16 judges whether this information is stored in a prefetch memory 26 or not and when it is stored, the processor 16 stores this data information from the prefetch memory 26 into the cache memory 12. When the target data information is not stored in the prefetch memory 26, the processor 16 requests this data information from a system memory 30 through a system bus 28. Afterwards, when a BIU 18 inputs the received data information, the processor 16 stores the information from a read register 24 into the cache memory 12.

72. 发明专利

JPH07114498A MICROPROCESSOR 失效
公开(公告)号：JPH07114498A
公开(公告)日：1995-05-02
申请号：JP25846693
申请日：1993-10-15
申请人： TOSHIBA CORP
发明人： ONAINO SEIJI , YAGUCHI TOSHIYUKI , HISAMA YURIKO
IPC分类号： G06F12/06 , G06F9/30 , G06F9/312 , G06F9/46
摘要： PURPOSE:To provide a microprocessor in which the execution waiting tame of a following instruction accompanying the switching of a bank can be reduced. CONSTITUTION:This microprocessor is constituted of register banks FR1-FR4, a current bank pointer CBP which holds the position information of the saving area or that of the restoring area of the contents of the register banks, and a bank size designation register BS which designates the bank size in saving/ restoration. When the current bank pointer is designated as the destination operand of a prescribed instruction, the bank size designated by the bank size destination register BS is saved to a built-in RAM based on the content cbp of the current bank pointer at designated time, and the content of the current bank point is rewritten based on the intruction, and the information of bank size is restored from the built-in RAM to the bank register based on the content cbp' of the current bank pointer after rewrite.

73. 发明专利

JPH05143335A METHOD FOR ACCELERATING OPERATING SPEED OF PROCESSOR 失效
公开(公告)号：JPH05143335A
公开(公告)日：1993-06-11
申请号：JP13867091
申请日：1991-05-15
申请人： SUN MICROSYSTEMS INC
发明人： ERITSUKU HAATOUIGU JIENSEN
IPC分类号： G06F9/312 , G06F9/34 , G06F9/38
摘要： PURPOSE: To improve an operating speed by deciding the difference of the effective addresses of two load instructions indexed by the address of the load instruction, and adding the difference in order to obtain the predictive address of the next load instruction. CONSTITUTION: Each time an instruction for executing a predictive operation reaches a decoding stage, a predictive table 12 is indexed by using the address of the instruction in order to retrieve the entry of an LEA and an NLEA. The tag of a line to which access is performed is compared with the tag of the instruction, and when an upper bit is the same and a state bit is 1, the values of the effective addresses of the LEA string and the NLEA string are retrieved, and transferred to a subtracter. The subtracter supplies the difference of two sets of lower bits as an output value to an adder with the front effective address. The predicted effective address is compared with the effective address of a load instruction, an enable output is supplied to an AND gate, and information in the predictive address can be used by an instruction following the load instruction.

74. 发明专利

JPH04260930A DATA PROCESSOR 失效
公开(公告)号：JPH04260930A
公开(公告)日：1992-09-16
申请号：JP523091
申请日：1991-01-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： YOSHIDA TOYOHIKO
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312 , G06F12/00
摘要： PURPOSE:To offer a data processor capable of loading plural data from a memory to a register by one processing and highly efficiently processing an instruction for storing data from the register to the memory with respect to a data processor for decomposing an instruction for transferring plural data between register files and the memory into plural transfer instructions by a decoder and executing the pipeline processing of the decomposed instructions. CONSTITUTION:The data processor is provided with an instruction decoding part 112 for decomposing both of an instruction for loading plural data from the memory to the register and an instruction for storing plural data from the register in the memory to plural processing units and decoding respective processing units, an instruction execution part connected to an external memory through a data bus to execute instructions and an instruction execution control part for controlling the execution of instructions by the instruction execution part in accordance with respective processing units outputted from the decoding part 112 and the decoding processing of the decoding part 112 to output respective processing units and the instruction execution of the instruction execution part based upon the outputted processing units are mutually overlapped and executed in accordance with the principle of pipeline processing.

75. 发明专利

JPS63501453A 失效
公开(公告)号：JPS63501453A
公开(公告)日：1988-06-02
申请号：JP50631986
申请日：1986-11-03
IPC分类号： G06F12/10 , G06F9/312 , G06F12/02

76. 发明专利

JPS6355636A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6355636A
公开(公告)日：1988-03-10
申请号：JP19886986
申请日：1986-08-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , HASHIMOTO KOJI , KAWASAKI IKUYA , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO
IPC分类号： G06F9/46 , G06F9/30 , G06F9/312 , G06F17/30
摘要： PURPOSE:To retrieve a queue at a high speed by obtaining the head address of a desired entry by means of a queue retrieving instruction and its preceding register setting instruction. CONSTITUTION:An LSI chip 1 forming a microprocessor contains a micro ROM 2 storing a microprogram. The ROM 2 receives an access from a microaddress generating circuit 5 and delivers successively microinstruction. A control signal is produced to an executing unit 6 by a microinstruction code. A queue retrieving instruction is newly added to the microinstruction; while the head address of a retrieval start entry needed for retrieval of the queue, the comparison value serving as the selecting conditions and the offset value of the retrieving data set within an entry are supplied previously to a prescribed register. Then the queue retrieving instruction is carried out.

77. 发明专利

JPS6231378B2 失效
公开(公告)号：JPS6231378B2
公开(公告)日：1987-07-08
申请号：JP11895280
申请日：1980-08-27
申请人： SHARP KK
发明人： TOMINAGA MEGUMI
IPC分类号： G06F9/30 , G06F9/06 , G06F9/312 , G06F15/02

78. 发明专利

JPS60142743A INTERNAL BUS SYSTEM 失效
公开(公告)号：JPS60142743A
公开(公告)日：1985-07-27
申请号：JP24256384
申请日：1984-11-19
申请人： IBM
发明人： DEERU EDOWAADO FUISUKU , ROORENSU UIRIAMU PERIIRA , JIYOOJI RADEIN
IPC分类号： G06F7/00 , F02B75/02 , G06F9/30 , G06F9/312 , G06F9/38 , G06F13/36

79. 发明专利

JPS5955538A Controller of electronic equipment 失效
标题翻译：电子设备控制器
公开(公告)号：JPS5955538A
公开(公告)日：1984-03-30
申请号：JP16508982
申请日：1982-09-24
申请人： Casio Comput Co Ltd
发明人： IBA AKIO
IPC分类号： G06F9/26 , G06F9/22 , G06F9/312 , G06F9/32 , G10H7/00
CPC分类号： G06F9/30043
摘要： PURPOSE:To simplify the constitution of a memory, by providing an address means consisting of an adder circuit and a latch circuit and a selection means consisting of plural gate circuits, to read out and process the data after setting it to a program region. CONSTITUTION:When a data storing instruction is supplied, a control signal generating part CONT delivers a pseudo instruction signal. Then an AND3 is turned on and an FF1 is set to deliver an ''NOP'' signal. The address data of an Rg3 existing on an address line is stored in an RAM through a Gg2 which is turned on by the output GOST of an NOR1 and via half adders HA2 and an Rg10. When a Gg5 is turned on by the output of an AND7, the data of 4 bits given from the Rg3 is fed to the RAM through a bus line. Here an R/W signal is delivered from the CONT to write the 4-bit data to an address designated by an address input ADD. Thereafter, the writing is successively carried out in the same way.
摘要翻译：目的：为了简化存储器的结构，通过提供由加法器电路和锁存电路组成的地址装置和由多个门电路组成的选择装置，在将其设置到程序区域之后读出并处理数据。构成：当提供数据存储指令时，控制信号生成部CONT发送伪指令信号。然后打开一个AND3，一个FF1被设置为提供一个“NOP”信号。存在于地址线上的Rg3的地址数据通过由NOR1的输出GOST和半加法器HA2和Rg10导通的Gg2存储在RAM中。当通过AND7的输出打开Gg5时，从Rg3给出的4位的数据通过总线被馈送到RAM。这里，从CONT发送R / W信号，以将4位数据写入由地址输入ADD指定的地址。此后，以相同的方式依次进行写入。

80. 发明专利

JPS58213323A Mark signal generating circuit 失效
标题翻译：标记信号发生电路
公开(公告)号：JPS58213323A
公开(公告)日：1983-12-12
申请号：JP9482382
申请日：1982-06-04
申请人： Hitachi Ltd
发明人： MORIKAWA TAKASHI
IPC分类号： G06F13/12 , G06F9/312
CPC分类号： G06F9/30043
摘要： PURPOSE:To save the amount of hardware, by providing two pointer effectiveness displays for discriminating whether a start pointer and an end pointer are used or not. CONSTITUTION:A mark signal generating circuit is provided with a start pointer effectiveness indicating flip-flop 7, an end pointer effectiveness displaying flip- flop 8, an AND circuit 9 and an OR circuit 10. A value of a start pointer 1 is inputted to an A pattern generator 3 as it is from the AND circuit 9 when the flip-flop 7 is 1, and a value of all 0 is inputted as the start pointer when the flip-flop 7 is 0. Further, a value of an end pointer 2 is inputted to a B pattern generator 4 as it is when the flip-flop 8 is 1, and all 1 is inputted as the end pointer when 0. Thus, two pointers are not required at the memory transfer on the halfway.
摘要翻译：目的：为了节省硬件量，通过提供两个指针有效性显示来区分是否使用起始指针和结束指针。构成：标记信号发生电路具有指示触发器7的起始指针效能，结束指针有效性显示触发器8，AND电路9和OR电路10.起始指针1的值被输入到当触发器7为1时，来自AND电路9的A模式发生器3，并且当触发器7为0时，输入全0的值作为开始指针。此外，结束的值当触发器8为1时，指针2被直接输入到B模式发生器4，并且当0时，指针2作为结束指针输入。因此，在中途的存储器传送中不需要两个指针。

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