专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明专利

JP2012074131A Content addressable memory with read/write function causing no interruption of continuous retrieval cycle 有权
标题翻译：具有读/写功能的内容可寻址存储器，不会导致连续检索周期中断
公开(公告)号：JP2012074131A
公开(公告)日：2012-04-12
申请号：JP2011260527
申请日：2011-11-29
申请人： Core Networks Llc , コア・ネットワークス・リミテッドライアビリティカンパニーCore Networks LLC
发明人： GIBSON G F RANDALL , RADU AVRAMESCU
IPC分类号： G06F17/30 , G11C15/04 , G11C15/00 , G11C29/00 , G11C29/14 , G11C29/26
CPC分类号： G06F7/74 , G11C15/00 , G11C15/04 , G11C29/14 , G11C29/26 , G11C29/816 , G11C2029/2602
摘要： PROBLEM TO BE SOLVED: To provide a content addressable memory (CAM).SOLUTION: The CAM includes a retrieval port 102b for performing retrieval operation in each clock cycle, and a maintenance port 103a for writing and reading data at an address position of the content addressable memory. Further, an interlock signal is available, and transmitted from the retrieval port to the maintenance port to set the time when the data is written to and read out of the content addressable memory, and consequently the retrieval operation is continuous in the respective clock cycles without being interrupted. It is preferred that the interlock signal is transmitted at the end time of the retrieval operation and at the start time of retrieval precharge operation. The maintenance port is configured to set up the writing operation at the start time of the clock cycles and to perform the writing operation at the end time of the retrieval operation and at the start of the retrieval precharge operation.
摘要翻译：要解决的问题：提供内容可寻址存储器（CAM）。解决方案：CAM包括用于在每个时钟周期中执行检索操作的检索端口102b，以及用于在内容可寻址存储器的地址位置写入和读取数据的维护端口103a。此外，互锁信号可用，并且从检索端口传送到维护端口以设置数据被写入和读出内容可寻址存储器的时间，因此检索操作在各个时钟周期中是连续的，而没有被中断优选地，在检索操作的结束时间和检索预充电操作的开始时间期间发送互锁信号。维护端口被配置为在时钟周期的开始时间设置写入操作，并且在检索操作的结束时和在检索预充电操作开始时执行写入操作。版权所有（C）2012，JPO＆INPIT

72. 发明专利

JP4570891B2 Storage device 有权
公开(公告)号：JP4570891B2
公开(公告)日：2010-10-27
申请号：JP2004097458
申请日：2004-03-30
申请人：ルネサスエレクトロニクス株式会社
发明人：靖宏中村 , 千晶品川 , 信介浅利 , 敦白石 , 賢樹金森
IPC分类号： G06F12/16 , G11C29/00 , G11C29/26
CPC分类号： G11C29/883 , G11C11/5635 , G11C16/04 , G11C29/26 , G11C29/76 , G11C29/88
摘要： The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

73. 发明专利

JP2009104605A Histogram generation with bank for improved memory access performance 审中-公开
标题翻译：具有改进的存储器访问性能的银行的组织生成
公开(公告)号：JP2009104605A
公开(公告)日：2009-05-14
申请号：JP2008271099
申请日：2008-10-21
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： JONES MICHAEL FRANK , KUSHNICK ERIC BARR
IPC分类号： G06F12/06
CPC分类号： G11C29/26 , G11C29/56 , G11C2029/2602 , H03M1/1071
摘要： PROBLEM TO BE SOLVED: To generate a histogram using multiple banks for improved memory access performance.
SOLUTION: Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data is captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：使用多个存储体生成直方图，以提高存储器访问性能。解决方案：尽管相同的地址线被提供给每个存储体，但是地址控制逻辑确保每个连续的RMW周期由不同的存储体来处理，从而可以在一个存储体中启动另一个RMW周期，而先前的RMW周期仍然是在另一家银行执行。通过以环绕方式交错或定位RMW周期的开始，每个直方图单元都分布在多个存储区中，但是测试可以比仅使用单个存储单元更快地进行。在捕获直方图数据之后，可以将与特定仓相关联的每个存储区中的存储区域加在一起，以计算该仓的总计数。版权所有（C）2009，JPO＆INPIT

74. 发明专利

JP4184036B2 Semiconductor memory device and a method of testing the same 有权
公开(公告)号：JP4184036B2
公开(公告)日：2008-11-19
申请号：JP2002311297
申请日：2002-10-25
申请人：株式会社ルネサステクノロジ
发明人：彦士半治 , 康浩松井
IPC分类号： G01R31/28 , G11C29/12 , G11C11/413 , G11C29/00 , G11C29/26
CPC分类号： G11C29/26 , G11C11/41

75. 发明专利

JP4129187B2 Address generating method for semiconductor memory test system and failure analysis 有权
公开(公告)号：JP4129187B2
公开(公告)日：2008-08-06
申请号：JP2002590367
申请日：2002-05-16
申请人：株式会社アドバンテスト
发明人：知之山根
IPC分类号： G11C29/56 , G01R31/28 , G01R31/3183 , G11C29/10 , G11C29/26
CPC分类号： G11C29/56004 , G11C29/26 , G11C29/56 , G11C2029/5606

76. 发明专利

JP3857697B2 Semiconductor integrated circuit, the test method of the semiconductor memory device and semiconductor memory device 有权
公开(公告)号：JP3857697B2
公开(公告)日：2006-12-13
申请号：JP2004087166
申请日：2004-03-24
申请人：株式会社東芝
发明人：敏正行川
IPC分类号： G01R31/28 , G11C5/00 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34 , H01L27/10 , H03K5/00 , H03K17/00 , H03K17/16
CPC分类号： G11C7/1051 , G11C7/1012 , G11C11/401 , G11C29/06 , G11C29/1201 , G11C29/26 , G11C29/40 , G11C2029/2602

77. 发明专利

JP3841535B2 Semiconductor memory device 失效
公开(公告)号：JP3841535B2
公开(公告)日：2006-11-01
申请号：JP33831797
申请日：1997-12-09
申请人：富士通株式会社
发明人：淳畠山
IPC分类号： G01R31/28 , G11C29/04 , G11C29/00 , G11C29/26 , G11C29/34
CPC分类号： G11C29/80 , G11C29/26

78. 发明专利

JP2006120241A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006120241A
公开(公告)日：2006-05-11
申请号：JP2004307046
申请日：2004-10-21
申请人： Toshiba Corp , 株式会社東芝
发明人： ITOGA NAOKO , IWAI HITOSHI
IPC分类号： G11C29/12 , G01R31/28 , G11C11/401 , G11C29/34
CPC分类号： G11C29/26 , G11C2029/2602
摘要： PROBLEM TO BE SOLVED: To simultaneously test a plurality of memory blocks having different address spaces.
SOLUTION: The semiconductor device 1 is provided with: a first memory block MCR1 having the first address space; a second memory block MCR2 having the second address space smaller than the first address space; and a test circuit 2 for supplying test addresses and test control signals to the first and second memory blocks and for simultaneously testing the first and second memory blocks. The second memory block MCR2 includes a storage circuit 3a for storing the address corresponding to the second address space and a control circuit 3b for inactivating the test control signal when the address beyond the second address space is designated by the test circuit 2.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：同时测试具有不同地址空间的多个存储块。解决方案：半导体器件1具有：具有第一地址空间的第一存储块MCR1; 具有小于第一地址空间的第二地址空间的第二存储块MCR2; 以及用于向第一和第二存储器块提供测试地址和测试控制信号并且同时测试第一和第二存储器块的测试电路2。第二存储器块MCR2包括用于存储对应于第二地址空间的地址的存储电路3a和用于当由测试电路2指定超过第二地址空间的地址时停止测试控制信号的控制电路3b。版权所有（C）2006，JPO＆NCIPI

79. 发明专利

JP2006114192A Data output compression circuit for testing cell in bank and its method 有权
标题翻译：用于银行测试单元的数据输出压缩电路及其方法
公开(公告)号：JP2006114192A
公开(公告)日：2006-04-27
申请号：JP2004377152
申请日：2004-12-27
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： LEE CHANG-HYUK
IPC分类号： G11C29/34 , G11C11/401 , G11C11/407
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26
摘要： PROBLEM TO BE SOLVED: To reduce layout of semiconductor memory elements by sharing one data output compression circuit with a plurality of banks. SOLUTION: Disclosed is a data output compression circuit for testing a cell in the bank. In a semiconductor memory element including a plurality of the bank parts which share a parallel plurality of global input/output lines and can store data, the element includes a multiple clock generating part for receiving a test mode signal applied from the outside and an internal clock signal generated corresponding to an external clock and outputting a first control clock and a second control clock, an arithmetic part for logically coupling data placed on the parallel plurality of global input/output lines, and a switching part controlled by the test mode signal, the first control clock, and the second control clock, and outputting the data placed on a test global input/output line connected to the output side of the arithmetic part. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过与多个存储体共享一个数据输出压缩电路来减少半导体存储元件的布局。解决方案：公开了一种用于测试银行中的单元的数据输出压缩电路。在包括共享并行多个全局输入/输出线并且可以存储数据的多个存储体部分的半导体存储元件中，元件包括用于接收从外部施加的测试模式信号的多时钟产生部分和内部时钟产生对应于外部时钟的信号并输出第一控制时钟和第二控制时钟，用于逻辑耦合放置在并行多个全局输入/输出线并行的数据的运算部分和由测试模式信号控制的切换部分，第一控制时钟和第二控制时钟，并且输出放置在连接到算术部分的输出侧的测试全局输入/输出线上的数据。版权所有（C）2006，JPO＆NCIPI

80. 发明专利

JP2005286345A Semiconductor device with a plurality of ground planes 审中-公开
标题翻译：具有多个地面平面的半导体器件
公开(公告)号：JP2005286345A
公开(公告)日：2005-10-13
申请号：JP2005125649
申请日：2005-03-28
申请人： Inapac Technology Inc , イナパックテクノロジーインコーポレイテッド
发明人： HO FAN
IPC分类号： H01L23/12 , G01R31/28 , G01R31/3161 , G01R31/317 , G01R31/3185 , G11C29/26 , G11C29/48 , H01L23/02 , H01L23/50 , H01L25/065 , H01L25/18 , H01L25/04
CPC分类号： B82Y10/00 , G01R31/3161 , G01R31/31715 , G01R31/318505 , G11C11/401 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/50 , H01L25/0655 , H01L2924/0002 , H01L2924/01079 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a multi-chip module (MCM) having a plurality of ground planes/layers.
SOLUTION: Each integrated circuit (IC) chip of MAM has its own ground plane on a substrate in the MCM. This MCM structure smoothly performs a separate test for each IC without affecting other chips or being affected by other chips. Further, This MCM structure facilitates a test of mutual interconnection and interconnection between two or more chips.
COPYRIGHT: (C)2006,JPO&NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式