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1. 发明专利

KR102224843B1 KR102224843B1 - Memory device and test system having the same 有权
公开(公告)号：KR102224843B1
公开(公告)日：2021-03-08
申请号：KR1020140133453A
申请日：2014-10-02
申请人： 삼성전자주식회사
发明人： 박성훈
IPC分类号： G11C29/04
CPC分类号： G11C29/44 , G11C29/06 , G11C29/26 , G11C2029/2602
摘要： 본 발명의 하나의 실시형태에 따른 테스트 시스템(test system)은 복수의 메모리 칩들 그리고 상기 복수의 메모리 칩들 각각을 동시에 테스트하는 테스터(tester)를 포함하며, 상기 복수의 메모리 칩들 각각은 적어도 하나의 불량 속성을 포함하는 셀 어레이 그리고 상기 셀 어레이로 스트레스를 인가하기 위한 적어도 하나의 BIST 로직을 포함하고, 상기 복수의 메모리 칩들 각각은 독립적으로 상기 적어도 하나의 BIST 로직을 이용하여 서로 상이한 스트레스 프로세스를 진행한다.

2. 发明专利

JP5860545B2 フローティングゲートを有する不揮発性メモリセルのデータ保持力を試験する方法有权
标题翻译：方法的非易失性存储单元的测试数据保留具有浮栅
公开(公告)号：JP5860545B2
公开(公告)日：2016-02-16
申请号：JP2014541085
申请日：2012-10-22
申请人：シリコンストーリッジテクノロージーインコーポレイテッド , SILICON STORAGE TECHNOLOGY, INC.
发明人：マルコフヴィクター , ユジョン−ウォン , バンサルサティシュ , コトフアレクサンダー
IPC分类号： G11C29/56
CPC分类号： G11C29/50 , G11C29/06 , G11C29/50004 , G11C29/50016 , G11C16/00 , G11C16/349

3. 发明专利

JP5319641B2 Diagnostic circuit and semiconductor integrated circuit 有权
公开(公告)号：JP5319641B2
公开(公告)日：2013-10-16
申请号：JP2010231088
申请日：2010-10-14
申请人：株式会社東芝
发明人：文彦橘
IPC分类号： G11C29/06
CPC分类号： G11C29/06 , G11C11/41 , G11C29/50
摘要： According to one embodiment, a certain amount of data is held in the memory cells, and after a state of the data held in the memory cell is transferred into an indefinite state, data autonomously held in the memory cell is read, and a change of the threshold voltage of transistors is diagnosed on the basis of the distribution of the data autonomously held in the memory cell.

4. 发明专利

JP2012113776A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012113776A
公开(公告)日：2012-06-14
申请号：JP2010260491
申请日：2010-11-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： RIHO YOSHIRO , NODA HIROMASA , SAKUMA KAZUKI
IPC分类号： G11C29/06
CPC分类号： G11C29/00 , G11C29/02 , G11C29/06 , G11C29/12005 , G11C29/28 , G11C29/50 , G11C2029/1202 , G11C2029/2602
摘要： PROBLEM TO BE SOLVED: To increase the number of word lines to be simultaneously started in a stress test.SOLUTION: A semiconductor device includes: a memory cell array 30 which is divided into a plurality of memory cell mats MAT by a plurality of sense amplifier columns 32, and each of which includes a plurality of word lines WL; and a test circuit 25 which performs test control for simultaneously starting the plurality of word lines WL each of which is included in a plurality of selected memory cell mats MAT which are not adjacent to one another among the plurality of memory cell mats MAT. According to the present invention, loads to a driver circuit for driving the word lines or a power supply circuit for supplying operation voltage to the driver circuit are reduced in comparison with the case of starting many word lines in one memory cell mat since the memory cell mats MAT in which the plurality of word lines WL are started are distributed. As a result, it becomes possible to simultaneously start more word lines.
摘要翻译：要解决的问题：增加在压力测试中同时开始的字线数量。解决方案：半导体器件包括：存储单元阵列30，其通过多个读出放大器列32被分成多个存储单元阵列MAT，并且每个包括多个字线WL; 以及测试电路25，其执行用于同时启动多个字线WL的测试控制，每个字线WL被包括在多个存储单元垫MAT中彼此不相邻的多个选择的存储单元矩阵MAT中。根据本发明，与从一个存储单元垫开始多个字线的情况相比，与用于驱动字线的驱动电路的负载或用于向驱动器电路提供工作电压的电源电路相比减少了，因为存储单元散布有多个字线WL的垫MAT分布。结果，可以同时开始更多的字线。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012084208A Diagnosis circuit and semiconductor integrated circuit 有权
标题翻译：诊断电路和半导体集成电路
公开(公告)号：JP2012084208A
公开(公告)日：2012-04-26
申请号：JP2010231088
申请日：2010-10-14
申请人： Toshiba Corp , 株式会社東芝
发明人： TACHIBANA FUMIHIKO
IPC分类号： G11C29/06 , G11C29/12
CPC分类号： G11C29/06 , G11C11/41 , G11C29/50
摘要： PROBLEM TO BE SOLVED: To diagnose the degree of variations in a threshold voltage of a transistor due to PBTI or NBTI.SOLUTION: Definite data is held in a memory cell 1 and then the data held in the memory cell 1 is switched to a indefinite state. Thereafter the data autonomously held in the memory cell 1 is read out. Based on distribution of the data held autonomously in the memory cell 1, variations in a threshold voltage of a transistor are diagnosed.
摘要翻译：要解决的问题：诊断由于PBTI或NBTI引起的晶体管的阈值电压的变化程度。解决方案：将确定的数据保存在存储单元1中，然后将保存在存储单元1中的数据切换到不确定状态。此后，读出自主保存在存储单元1中的数据。基于在存储单元1中自主保持的数据的分布，诊断晶体管的阈值电压的变化。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2009053130A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009053130A
公开(公告)日：2009-03-12
申请号：JP2007222095
申请日：2007-08-29
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： JINBO TOSHIKATSU
IPC分类号： G01R31/28 , G11C29/06 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31718 , G11C29/06 , G11C29/48 , G11C29/50
摘要： PROBLEM TO BE SOLVED: To provide a technique to determine from outside whether or not a stress test was actually performed.
SOLUTION: A semiconductor device (1) includes a stress test circuit (11) and a stress test determination circuit (12). The stress test circuit (11) outputs control signals (TM1-TM3) for performing a stress test to a test object (2) and the stress test determination circuit (12). The stress test determination circuit (12) outputs the determination result indicating whether or not the stress test has been performed based on the control signals (TM1-TM3).
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种从外部确定是否实际进行压力测试的技术。解决方案：半导体器件（1）包括应力测试电路（11）和应力测试确定电路（12）。应力测试电路（11）将用于进行应力测试的控制信号（TM1-TM3）输出到测试对象（2）和应力测试确定电路（12）。应力测试确定电路（12）根据控制信号（TM1-TM3）输出指示是否执行了应力测试的确定结果。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2009043340A Internal power source circuit 有权
标题翻译：内部电源电路
公开(公告)号：JP2009043340A
公开(公告)日：2009-02-26
申请号：JP2007207500
申请日：2007-08-09
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： TAKEUCHI ATSUSHI
IPC分类号： G11C29/06 , G01R31/28 , G11C11/401 , G11C11/4074
CPC分类号： G11C29/12 , G11C5/145 , G11C11/401 , G11C29/06 , G11C29/12005
摘要： PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit in which defect can be actualized without affecting to operation of an internal circuit in a burn-in acceleration test.
SOLUTION: The internal power source circuit for generating internal voltage based on reference voltage has an external power source terminal to which an external power source having a first potential is applied during normal operation and an external power source having a second potential being higher than the first potential is applied during the burn-in acceleration test, a reference voltage generating unit generating reference voltage from the external power source, and an internal voltage generating unit generating internal voltage based on reference voltage. The reference voltage generating unit generates normal reference voltage which does not depend on a potential of the external power source during normal operation, and generates first burn-in reference voltage depending on a potential of the external power source and second burn-in reference voltage having a potential being same as the normal reference voltage during burn-in acceleration test.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种参考电压发生电路，其中可以实现缺陷而不影响老化加速度试验中的内部电路的操作。解决方案：用于产生基于参考电压的内部电压的内部电源电路具有在正常操作期间施加具有第一电位的外部电源的外部电源端子和具有第二电位的外部电源较高在老化加速试验中施加第一电位，从外部电源产生参考电压的基准电压产生单元和基于参考电压产生内部电压的内部电压产生单元。参考电压产生单元在正常操作期间产生不依赖于外部电源的电位的正常参考电压，并且根据外部电源的电位和第二老化基准电压产生第一老化参考电压，在老化加速试验中的电位与正常参考电压相同。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP3691655B2 Controlling method and circuit of the redundant memory cells of the memory integrated circuits, and memory integrated circuits 失效
公开(公告)号：JP3691655B2
公开(公告)日：2005-09-07
申请号：JP5724398
申请日：1998-03-09
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：李載雄 , 柳濟煥
IPC分类号： G11C16/06 , G11C7/00 , G11C29/00 , G11C29/04 , G11C29/06
CPC分类号： G11C29/24 , G11C29/06 , G11C29/785 , G11C29/802

9. 发明专利

KR102226106B1 KR102226106B1 - Negative bias thermal instability stress testing for static random access memory (sram) 有权
公开(公告)号：KR102226106B1
公开(公告)日：2021-03-09
申请号：KR1020140111518A
申请日：2014-08-26
申请人： 시놉시스, 인크.
发明人： 자밀 카와 , 총-쾅 헨리 예 , 시-야오 크리스틴 선 , 레이몬드 탁-호이 렁
IPC分类号： G01R31/26
CPC分类号： G11C29/06 , G11C11/41 , G11C2029/5002
摘要： 일 실시형태에서, SRAM 어레이의 일부분은 어레이의 모든 비트에서 "1" 을 첫번째로 기록한 다음, 후속하여 미러링된 비트 라인 전류에 의해 구동되는 링 발진기를 이용하여 어레이의 관련 파라미터들의 평가를 행함으로써 스트레스를 받으며, 링 발진기는 SRAM 의 비트 라인의 라인에는 없다. 그 후 다른 어레이 부분이 어레이의 모든 비트에 "0"을 기록한 후 스트레스를 받는다. 그 후, 평가 절차가 반복된다.

10. 发明专利

JPWO2014045512A1 不揮発性記憶装置およびその制御方法有权
标题翻译：非易失性存储装置及其控制方法
公开(公告)号：JPWO2014045512A1
公开(公告)日：2016-08-18
申请号：JP2014536567
申请日：2013-08-09
申请人：学校法人中央大学 , 学校法人中央大学
发明人：友こ岩崎 , 友こ岩崎 , 幸祐宮地 , 幸祐宮地 , 竹内　健 , 健竹内
IPC分类号： G11C13/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C29/06 , G11C2013/0047 , G11C2013/0057 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , G11C2213/82
摘要：抵抗記憶素子にディスターブが発生することを防ぎつつ、読み出し速度や書き込み速度を向上させる。本発明に係る不揮発性記憶装置100は、不揮発性の抵抗記憶素子を少なくとも1つ備えるメモリ102と、抵抗記憶素子に高抵抗状態または低抵抗状態を書き込む制御部104とを備え、制御部104は、高抵抗状態の書き込み後の検証動作時に抵抗記憶素子に印加するバイアスの方向と、低抵抗状態の書き込み後の検証動作時に抵抗記憶素子に印加するバイアスの方向とを逆方向とする。
摘要翻译：同时防止干扰在所述电阻式存储器元件产生，提高了读出速度和写入速度。根据本发明的非易失性存储器装置100包括存储器102，其包括非易失性中的至少一个电阻式存储器元件，以及控制单元104到高或低电阻状态写入到电阻式存储器元件，则控制单元104 到写入的高电阻状态的，和写入在低电阻状态和相反的方向之后的验证操作期间施加到电阻式存储器元件的偏压的方向之后的验证操作期间施加到电阻式存储器元件的偏置的方向。

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