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71. 发明专利

JPH0287394A NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0287394A
公开(公告)日：1990-03-28
申请号：JP23686988
申请日：1988-09-21
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , TANAKA SUMIO , MIYAMOTO JUNICHI , ATSUMI SHIGERU
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent the generation of miswriting of data by controlling a MOS transistor in N-channel inserted between a bit line and a low potential temporarily in an energized condition when the supply of the power voltage of a high potential to a power terminal is started, and discharging a bit line potential to the low potential. CONSTITUTION:When the supply of a second high power voltage VPP to a power terminal 15 is started, a MOS transistor 21 in N-channel inserted between bit lines BL1-BLn and a first low potential power voltage VCC is temporarily controlled in the energized condition, and after the start of the supply of the second power voltage VPP, the bit lines BL1-BLn potentials charged at the second power voltage VPP are discharged to the low potential. Thus, the generation of the miswriting of the data can be prevented.

72. 发明专利

JPH01290197A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01290197A
公开(公告)日：1989-11-22
申请号：JP11969988
申请日：1988-05-17
申请人： TOSHIBA CORP
发明人： ATSUMI SHIGERU , TANAKA SUMIO , MIYAMOTO JUNICHI , OTSUKA NOBUAKI , IMAMIYA KENICHI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To improve reliability by connecting a leak current generating circuit to an internal power source node and causing a current, which is suited to the sub threshold current of a transistor for pressure fall, to flow in a prescribed condition. CONSTITUTION:A first leak current generating circuit 8 is provided between a first internal power source node N1 and a Vss potential terminal (grounding terminal) and a second leak current generating circuit 9 is provided between a second internal power source node N2 and the grounding terminal. the both leak current generating circuits 8 and 9 cause the leak currents, which are suited to the sub threshold currents of transistors 2 and 5 for pressure fall, to flow with being respectively correspondent. Then, the potential of the nodes N1 and N2 is prevented from over-rising. Thus, stress on a setting value is not loaded to the MOS transistor of the internal circuit and the reliability is improved.

73. 发明专利

JPH01235097A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01235097A
公开(公告)日：1989-09-20
申请号：JP5991088
申请日：1988-03-14
申请人： TOSHIBA CORP
发明人： MIYAMOTO JUNICHI , OTSUKA NOBUAKI , TANAKA SUMIO , ATSUMI SHIGERU
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To write information in a memory cell at a high speed and with high stability in the cases of the large capacity of a memory and of fining elements by using a P channel MOS transistor as an element which controls a write current to an ultraviolet ray erasion type memory cell that can be rewritten. CONSTITUTION:A P channel MOS transistor CS' is used as an element which controls the write current to an ultraviolet ray erasion type memory cell MC that can be rewritten. Thus the write current to be applied to the cell MC is controlled by the transistor CS' and therefore a writing action point is prescribed to a snap-back area of the characteristics of the MC without boosting the due gate voltage. Thus it is possible to write the information in the memory cell at a high speed and with high stability in the case of the large capacity of the memory and of fining elements.

74. 发明专利

JPS63293800A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63293800A
公开(公告)日：1988-11-30
申请号：JP13080587
申请日：1987-05-27
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAMIYA KENICHI , TANAKA SUMIO , MIYAMOTO JUNICHI , ATSUMI SHIGERU , OTSUKA NOBUAKI , IYAMA YUMIKO
IPC分类号： G11C29/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C17/00 , G11C29/12
摘要： PURPOSE:To secure a sufficient power supply margin by means of all access operation including normal reading operation by providing the titled memory with a circuit for changing a data reading reference in a reading mode and a program verify mode. CONSTITUTION:At the time of the program verify mode, a dummy cell 11 capable of applying earth potential to its gate is turned off and a reference potential generated at that time is expressed by V2. At the time normal reading, potential Vcc is applied to the gate of the dummy cell 11, the dummy cell 11 is turned on and generates a reference voltage shown by V1, then V1

75. 发明专利

JPS63188895A NONVOLATILE MEMORY 失效
公开(公告)号：JPS63188895A
公开(公告)日：1988-08-04
申请号：JP2100687
申请日：1987-01-31
申请人： TOSHIBA CORP
发明人： IMAMIYA KENICHI , TANAKA SUMIO , ATSUMI SHIGERU , OTSUKA NOBUAKI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To obtain a memory reading a data immediately without being affected with the charging of a gate electrode of a bit line selection transistor (TR) by supplying a different power voltage to a column decoder and a row decoder depending on data write and data read. CONSTITUTION:A column decoder 32 consists of a NAND circuit 321 and an output gate 322 and a power supply switching circuit 31 to them consists of MOS TRs 311, 312 and an inverter circuit 313. The power supply switching circuit 33 to them consists of MOS TRs 331, 332 and an inverter circuit 333. Moreover, supply lines 41, 42 having a power voltage Vpp or Vcc to the gate of the bit line selection TR 36 are separated from the supply line 43 and he word line 37 of the power voltage Vpp or Vcc to the control gate electrode of the memory cell 38 to quicken the leading of the cell 38.

76. 发明专利

JPS63170952A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63170952A
公开(公告)日：1988-07-14
申请号：JP297687
申请日：1987-01-09
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , TANAKA SUMIO , ATSUMI SHIGERU
IPC分类号： H01L21/822 , G11C11/401 , G11C11/409 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/10
摘要： PURPOSE:To prevent the level of a substrate from fluctuating and to stabilize the function of other peripheral circuits by a method wherein a power-supply line for an output buffer circuit is separated from a power-supply line for a peripheral circuit and a substrate of the output buffer circuit is connected to the power-supply line for the peripheral circuit. CONSTITUTION:A power-supply line 12 dor an output buffer circuit and a power- supply line 13 for a peripheral circuit, which are separated from each other, are connected to a VSS power-supply pad 11 ; a peripheral circuit which is composed of a CMOS is connected to the power-supply line 13 for the peripheral circuit; an output buffer circuit which is composed of a P-channel CMOS transistor T1' and an N-channel CMOS transistor T2' is connected to the power-supply line 12 for the output butter circuit. In this case, a P-type substrate of the N-channel transistor T2' is connected not to the power-supply line 12 for the output buffer circuit but to the power-supply line 13 for the peripheral circuit. An electric current flows to the power-supply line 12 for the output buffer circuit; as a result, even when the level of the VSS power supply fluctuates, the level of the substrate does not fluctuate simultaneously because the substrate is connected to the power-supply line 13 for the peripheral circuit.

77. 发明专利

JPS63164367A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63164367A
公开(公告)日：1988-07-07
申请号：JP30860986
申请日：1986-12-26
申请人： TOSHIBA CORP
发明人： ATSUMI SHIGERU , TANAKA SUMIO , SAITO SHINJI , OTSUKA NOBUAKI
IPC分类号： H01L27/06 , H01L21/331 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/78
摘要： PURPOSE:To prevent the generation of the dissolution of aluminum even when an element is fined, and to obtain a semiconductor device having high junction breakdown strength and proper to the improvement of the degree of integration by forming a contact hole into a zone positioned outside a first conductivity type high concentration region and shaping an electrode being in contact with a second conductivity type region through the contact hole. CONSTITUTION:A field insulating film 32 is formed onto a P-type silicon substrate 31. An oxide film 33 for protecting the surface is shaped through heat treatment, a photo-resist 34 is applied onto the whole surface, and the photoresists 34 are left selectively through patterning. An oxide film 38 for interlayer insulation is deposited onto the whole surface through a vapor growth method, and the oxide film 35 is etched selectively and contact holes 39 are each formed near each central position of N diffusion layers 37a, 37b. Aluminum is evaporated, and patterned, thus shaping electrodes 40a, 40b. Accordingly, a semiconductor device having the high junction breakdown strength of an input protective circuit section and proper to the elevation of the degree of integration is acquired by a simple manufacturing process.

78. 发明专利

JP2002217706A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002217706A
公开(公告)日：2002-08-02
申请号：JP2001007681
申请日：2001-01-16
申请人： TOSHIBA CORP
发明人： HATADA HIROSHI , OTSUKA NOBUAKI
IPC分类号： G11C11/413 , G11C11/407 , G11C11/409 , G11C11/417 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that eliminates the occurrence of an erroneous comparison result just after power-down control in programmable impedance control circuit so as to attain the power-down control by a stop clock. SOLUTION: In the semiconductor device that has a connection terminal to which an external resistor is connected, an output buffer having transistor(TR) group for external drive where TRs with different widths are connected in parallel, an output impedance control means that automatically adjusts the impedance of the output buffer depending on the resistance of the external resistor, and a power-down function, the output impedance control means has a dummy buffer similarly configured to the output buffer and a comparison means that compares a 1st current flowing through the connection terminal with a 2nd current flowing through the dummy buffer and controls the comparison means to be inoperative for a recovery period of the dummy buffer after the power-down function is released.

79. 发明专利

JP2002094366A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002094366A
公开(公告)日：2002-03-29
申请号：JP2000282482
申请日：2000-09-18
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI
IPC分类号： G11C17/18 , G11C7/10 , G11C11/417 , G11C16/06 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can match impedance with high accuracy by suppressing error in an operating voltage with respect to its fluctuations, when applying programmable impedance control to an output buffer circuit. SOLUTION: In the semiconductor device provided with an internal circuit section that realizes a prescribed operation and with the output buffer circuit that drives output data outputted from the internal circuit section to provide an output of the data to a data output terminal, the output buffer circuit is configured with the output buffer circuit having an output transistor(TR) group, that drives the data output terminal at a low level and an output pre-stage circuit group that drives the gate of the output TR group, and a power supply of the output pre-stage circuit group is driven by a 2nd power supply VDDQ for output drive, whose voltage is selected different from the voltage of a 1st power supply VDD that drives the internal circuit section.

80. 发明专利

JP2001267499A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001267499A
公开(公告)日：2001-09-28
申请号：JP2000070945
申请日：2000-03-14
申请人： TOSHIBA CORP
发明人： HATADA HIROSHI , OTSUKA NOBUAKI , HIRABAYASHI OSAMU
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device wherein increase of a chip area is suppressed and timing of a signal is adjusted in a chip or wafer state, with even a fine timing adjustment allowed. SOLUTION: There are provided a main wiring 5 and a sub-wiring 7 provided below the main wiring 5 and connected in parallel between first and second points A and B in the main wiring 5 which can be cut with laser. The width of the sub-wiring 7 is narrower than that of the main wiring 5, with the sub- wiring 7 so provided as to be hidden under the main wiring 5 when viewed from above.

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