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61. 发明专利

JPS58223854A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：JPS58223854A
公开(公告)日：1983-12-26
申请号：JP10740482
申请日：1982-06-22
申请人： Nec Corp
发明人： TANAKA YOSHITAKA
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To collect only effective memory contents in a short time and to contribute to troubleshooting when a fault is analyzed, by limiting the contents of a memory to a range of a latest access at a fault generating time point. CONSTITUTION:A data processor 2 extracts the access addresses to be given to a main storage device 5 from an arithmetic processor 4 and an input/output processor 6 out of an address register 31, sets these addresses to a buffer writing register 40 and then registers them to a prescribed position of an address buffer register 36 shown by a writing pointer 35. The new memory access addresses are registered successively to the register 36 together with the career. A service processor 1 gives an inidcation to a main diagnosis control circuit 37 to collect the hardware fault information of the processor 2 when a fault of the processor 2 is detected. Thus all types of information which are needed for the fault analysis are collected.
摘要翻译：目的：仅在短时间内收集有效的内存内容，并通过将故障内容的内容限制在故障生成时间点的最新访问范围，为故障分析时的故障排除做出贡献。构成：数据处理器2从地址寄存器31中的算术处理器4和输入/输出处理器6中提取要提供给主存储装置5的存取地址，将这些地址设置到缓冲器写入寄存器40，然后寄存器它们到写入指针35所示的地址缓冲器寄存器36的指定位置。新的存储器访问地址连同事业连续地登记到寄存器36。当检测到处理器2的故障时，服务处理器1给主诊断控制电路37给出收集处理器2的硬件故障信息。因此，收集故障分析所需的所有类型的信息。

62. 发明专利

JPS58219653A Information processor 失效
标题翻译：信息处理器
公开(公告)号：JPS58219653A
公开(公告)日：1983-12-21
申请号：JP10237482
申请日：1982-06-15
申请人： Nec Corp
发明人： FURUI TOSHIYUKI
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To suppress unnecessary fault occurrence and to improve the maintainability and reliability of an information processor, by reporting pieces of fault information detected by the fault detecting circuit of the information processor selectively or holding them as historical log information. CONSTITUTION:A control part 1 includes a fault detecting circuit and detected fault information is registered in a fault registering circuit 5a through a signal line 101. Its output is sent through a signal line 171 and set in a fault state from an OR gate 7 through an output 200. A fault occurring in a register circuit 2-B is registered in a circuit 5b through a line 102 and appears at the output 200 through a line 172 and the OR gate 7 to be set in the fault state. When the fault is reported from an editing circuit 2-E, a circuit 5e is set through an AND gate 23 and it appears at the output 200 from the OR gate 7 to be set in the fault state. However, a fault occurring when the circuit 2-E is in a free state is known by setting a history holding circuit 6e through the AND gate 33.
摘要翻译：目的：通过选择性地报告信息处理器的故障检测电路检测到的故障信息，或者将其保持为历史日志信息，来抑制不必要的故障发生，提高信息处理器的可维护性和可靠性。构成：控制部分1包括故障检测电路，并且检测到的故障信息通过信号线101被登记在故障登记电路5a中。其输出通过信号线路171发送，并从OR门7设置为故障状态，寄存器电路2-B中发生的故障通过线路102登记在电路5b中，并通过线路172和OR门7出现在输出端200处，使其成为故障状态。当从编辑电路2-E报告故障时，电路5e通过与门23设置，并且它出现在或门7的输出200处于故障状态。然而，当通过与门33设置历史保持电路6e时，电路2-E处于自由状态时出现的故障是已知的。

63. 发明专利

JPS58213356A Electronic computer system 失效
标题翻译：电子计算机系统
公开(公告)号：JPS58213356A
公开(公告)日：1983-12-12
申请号：JP9482582
申请日：1982-06-04
申请人： Hitachi Ltd
发明人： FUJISAKI HIROO , IGARASHI HIDEO , NINOMIYA KAZUHIKO
IPC分类号： G06F11/00 , G06F11/07 , G06F11/34
CPC分类号： G06F11/0703
摘要： PURPOSE:To attain ease of failure detection, by logging out data of a corresponding unit before the processing is executed by the clear operation when the software detects a failure of the hardware, for storing the content on a recording medium before the clearing. CONSTITUTION:When the processing failure of the 1st unit 10 executing a prescribed processing is detected, a clear operator 100 is issued to the unit 10 from an FF16 of the 2nd unit 12. This operator 100 is set to an FF22 via an AND circuit 18 and an OR circuit 20. Further, the 3rd unit 14 is connected to the unit 10 with an interruption request signal 102, an interruption receiving signal 104 and a clear command 106. A failure generated in the unit 10 is monitored with this unit 14 via FFs 24-1-24-N and the circuit 20. Before the clear processing is executed by the operator 100 at the unit 14, the logging out of the corresponding unit is executed, and after the content is stored on a recording medium, the clear command 106 is supplied to the unit 10.
摘要翻译：目的：为了便于故障检测，通过在软件检测到硬件故障之前通过清除操作执行处理之前登记相应单元的数据，用于在清除之前将内容存储在记录介质上。构成：当检测到执行规定处理的第1单元10的处理失败时，从第2单元12的FF16向单元10发出清除操作器100.该运算器100通过AND电路18被设定为FF22 和OR电路20.此外，第三单元14利用中断请求信号102，中断接收信号104和清除命令106连接到单元10.在该单元14中产生的故障通过该单元14经由 FF 24-1-24-N和电路20.在单元14中由操作者100执行清除处理之前，执行对应单元的注销，并且在将内容存储在记录介质上之后，清除命令106被提供给单元10。

64. 发明专利

JPS58207162A Conversation type processing system 失效
标题翻译：对流式加工系统
公开(公告)号：JPS58207162A
公开(公告)日：1983-12-02
申请号：JP9080882
申请日：1982-05-27
申请人： Fujitsu Ltd
发明人： SATOU TSUNEO
IPC分类号： G06F12/16 , G06F11/00 , G06F11/07 , G06F15/00
CPC分类号： G06F11/004 , G06F11/0703
摘要： PURPOSE:To ensure the work processing with high efficiency, by shunting the information of a screen in case an error is produced and restoring the shunted information after the error is released. CONSTITUTION:The working is discontinued if a work processing part 10 has an error. Then a control part 20 shunt the information displayed at a display 4, i.e., the contents of a refresh buffer 3 to a storage circuit 5. Then the error processing information accordant with the type of the error is stored in the buffer 3. A message is displayed at the display 4 to process the error. Thus an operator completes the error processing based on the message. After the error processing is over, the contents of the circuit 5 are restored to the buffer 3. As a result, the work performed at a time point when the error arises is displayed at the dispaly 4.
摘要翻译：目的：为了确保高效率的工作处理，通过在产生错误的情况下分流屏幕的信息，并在发布错误后恢复分流的信息。构成：如果工作处理零件10有错误，则停止工作。然后，控制部分20将显示器4上显示的信息（即，刷新缓冲器3的内容）分流到存储电路5.然后，将符合错误类型的错误处理信息存储在缓冲器3中。消息显示在显示器4处理该错误。因此，操作员根据消息完成错误处理。在错误处理结束之后，将电路5的内容还原到缓冲器3.结果，在显示4处显示出现错误发生时刻的工作。

65. 发明专利

JPS58203533A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS58203533A
公开(公告)日：1983-11-28
申请号：JP8762082
申请日：1982-05-24
申请人： Meidensha Electric Mfg Co Ltd
发明人： MINAGAWA MAKOTO
IPC分类号： G06F11/07 , G06F11/22 , G06F13/00 , G06F15/16 , G06F15/177
CPC分类号： G06F11/0745 , G06F11/0703 , G06F11/0724 , G06F11/22
摘要： PURPOSE:To secure the coupling between effective microprocessors through a bus, by providing a self-diagnosis function diagnosing whether the self-bus coupling part is normal or not, to each microprocessor and separating a defective bus driver element from the bus line. CONSTITUTION:Plural microprocessors 1-3 are coupled by a bus line 10 and a bus driver/receiver circuit 12 of each processor is connected to the line 10 through a contact 11A of a relay 11. The circuit 12 executes serial-parallel conversion for the parallel data from a serial port 13 coupled with an internal bus 14 and series data from the line 10. In addition, a self-diagnosis processing part 15 is connected the bus 14 to process the failure diagnosis of the self-bus coupling part by using a fixed period or the idle time of processing. When the failure of the coupling part is detected, the relay 11 is actuated through an I/O port 16, the circit 12 is separated from the line 10 and the failure is diaplayed on a failure diaplay 17 to secure bus coupling between other processors.
摘要翻译：目的：通过提供诊断自我总线耦合部分是否正常的自诊断功能，通过总线确保有效的微处理器之间的耦合，以及将有缺陷的总线驱动器元件与总线分离。构成：多个微处理器1-3通过总线10耦合，并且每个处理器的总线驱动器/接收器电路12通过继电器11的触点11A连接到线10.电路12执行串行并行转换来自与内部总线14耦合的串行端口13的并行数据和来自线路10的串行数据。此外，自诊断处理部分15连接总线14以通过使用来处理自总线耦合部分的故障诊断固定时间或空闲时间的处理。当检测到耦合部件的故障时，继电器11通过I / O端口16被致动，电路12与线路10分离，故障被丢弃在故障消除装置17上，以确保其它处理器之间的总线耦合。

66. 发明专利

JPS58186861A Error state log system 失效
标题翻译：错误状态记录系统
公开(公告)号：JPS58186861A
公开(公告)日：1983-10-31
申请号：JP7099582
申请日：1982-04-27
申请人： Fujitsu Ltd
发明人： KABEMOTO AKIRA , HIWATARI AKITO
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/0703
摘要： PURPOSE:To detect a logical error during debugging and to investigate the cause of a hardware trouble due to a fault of an IC, etc., speedily, by reading easily a hardware state when an error occurs out of a system monitoring device at optional time. CONSTITUTION:If an error occurs to a processing part, the output ERR of an error detector 21 turns on to operates an FF13 by its leading signal and its output is transmitted as a clock stop signal to the processing part to stop the basic clock of the processing part. The signal ERR, on the other hand, actuates an address data generation part 15 to vary address data at specific intervals of time and it is sent to a decoding circuit 10. The hardware state corresponding to the output of the circuit 10 is sent out through a data bus 8 and inputted to the data input terminal of an RAM23 for hardware state storage. The output ERON of the FF13 is supplied to the RAM23 through a write enable signal generating circuit 18. Consequently, the hardware state when the error occurs is monitored excellently.
摘要翻译：目的：在调试过程中检测到逻辑错误，并通过选择性的时间，通过读取系统监控设备发生错误，轻松读取硬件状态，迅速查看由于IC故障导致的硬件故障原因等原因。构成：如果处理部分发生错误，则误差检测器21的输出ERR导通，通过其前导信号操作FF13，并且其输出作为时钟停止信号发送到处理部分以停止处理部分的基本时钟处理部分。另一方面，信号ERR致动地址数据生成部分15以在特定时间间隔改变地址数据，并将其发送到解码电路10.对应于电路10的输出的硬件状态通过数据总线8，并输入到用于硬件状态存储的RAM23的数据输入端。通过写使能信号发生电路18将FF13的输出ERON提供给RAM23。因此，监视错误发生时的硬件状态。

67. 发明专利

JPS58185099A Semiconductor external storage controller 失效
标题翻译：半导体外部存储控制器
公开(公告)号：JPS58185099A
公开(公告)日：1983-10-28
申请号：JP6893582
申请日：1982-04-24
申请人： Toshiba Corp
发明人： KANEKO YASUO , KATOU KIYOSHI
IPC分类号： G06F12/16 , G06F11/07
CPC分类号： G06F11/0727 , G06F11/0703
摘要： PURPOSE:To prevent the generation of an incidental accident and to improve reliability of the titled controller, by providing a flip-flop which performs the reading control of an external storage device, a pulse generator, and the 1st and 2nd gates which deliver the 1st and 2nd reading requests respectively. CONSTITUTION:An external storage controller 2 checks a command given from a main body. When a command is detected, the controller 2 saves the contents of an address register 22 to a main control part 21 and at the same time resets the contents of a flip-flop 41 to stop the reading action to an external storage device. After a control is given based on the command, the contents saved to the part 21 are set again to the register 22. Then the flip-flop 41 is set. Thus a reading request is given to the external storage device via an AND gate 43 and an OR gate 44 with the pulse given from an oscillator 42. Then the reading data is checked and corrected and then written again to the same address. This can prevent an incidental accident at an address having a low frequency of access.
摘要翻译：目的：为了防止产生偶发事故并提高标题控制器的可靠性，通过提供执行外部存储装置，脉冲发生器和第1和第2门的读取控制的触发器，该第一和第二门提供第一和二读请求。构成：外部存储控制器2检查从主体给出的命令。当检测到命令时，控制器2将地址寄存器22的内容保存到主控制部分21，并且同时复位触发器41的内容以停止对外部存储装置的读取动作。在基于命令给出控制之后，将保存到部件21的内容再次设置到寄存器22，然后设置触发器41。因此，通过与门44和与门44以及从振荡器42给出的脉冲给予外部存储装置的读取请求。然后读取数据被检查和校正，然后再次写入相同的地址。这可以防止在访问频率低的地址发生意外事故。

68. 发明专利

JPS5769352A Collection system of fault information 失效
标题翻译：故障信息收集系统
公开(公告)号：JPS5769352A
公开(公告)日：1982-04-28
申请号：JP14161480
申请日：1980-10-09
申请人： Fujitsu Ltd
发明人： SHIMAZUE TSUTOMU , SHIMADA JIYUN
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0727 , G06F11/0703
摘要： PURPOSE:collect the fault information for a single information process system, by transferring the contents of a main storage to an external auxiliary storage device immediately before the function of the information process system is discontinued by a software fault and the system is actuated for initial start again. CONSTITUTION:A single information process system is formed with a processor CPU1, a main storage device MEM2, an external auxiliary storage device EMEM3 and a fault detector ALM4. In case a fault such as a bug of software, etc. arises, a fault is in the system is decided as long as the detector ALM4 is impossible to receive the timing signal from the CPU1 even in lapse of a certain period of time. Thus an interruption is applied to the CPU1 from the detector ALM4, and the CPU1 analyzes the factor of this interruption. Then the CPU1 loads the fault information collection program in the device EMEM3 to a part of the device MEM2, transfers the contents of the MEM2 to a magnetic tape controller MTC5 of the EMEM3 and records the fault information to a magnetic tape unit MTU6.
摘要翻译：目的：收集单个信息处理系统的故障信息，在信息处理系统的功能被软件故障中断之前，将主存储器的内容传送到外部辅助存储设备，系统启动初始启动再次。构成：单个信息处理系统由处理器CPU1，主存储装置MEM2，外部辅助存储装置EMEM3和故障检测器ALM4构成。在发生诸如软件错误等的故障的情况下，只要检测器ALM4即使经过一段时间也不可能从CPU1接收定时信号，则系统中的故障被确定。因此，从检测器ALM4向CPU1施加中断，CPU1分析该中断的因素。然后，CPU1将设备EMEM3中的故障信息收集程序加载到设备MEM2的一部分，将MEM2的内容传送到EMEM3的磁带控制器MTC5，并将故障信息记录到磁带单元MTU6。

69. 发明专利

JPS5764854A Storage device of state history 失效
标题翻译：国家历史存储装置
公开(公告)号：JPS5764854A
公开(公告)日：1982-04-20
申请号：JP14132680
申请日：1980-10-09
申请人： Nec Corp
发明人： TANAKA KAZUMASA
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0703 , G06F11/3466
摘要： PURPOSE:To realize an easy and high-speed process of diagnosis to a device to be observed, by storing successively the internal state and having a storing operation of state history for the time designated previously even after the prescribed stop conditions are detected. CONSTITUTION:A control circuit 120 replaces an address counter 140 every time a trace condition detecting circuit 110 detects the trace conditions. At the same time, the state history information 131 of a device to be observed is written into an address designated by the counter 140 of a storage circuit 130. When the conditions to complete the tracing action is detected by a stop condition detecting circuit 100, a signal 120 is delivered. The stop signal is delayed 152 by a delaying circuit 150 and by a time 151 that is previously designated. Then the tracing (state history storing) action is carried out. In such way, the tracing after detection of stop conditions to realize an easy and high-speed process of diagnosis to a device to be observed.
摘要翻译：目的：即使在检测到规定的停止条件之后，通过连续地存储内部状态并且具有对先前指定的时间的状态历史的存储操作来实现对待观察的装置的简单和高速诊断过程。构成：每当轨迹条件检测电路110检测到迹线条件时，控制电路120替换地址计数器140。同时，要观察的装置的状态历史信息131被写入由存储电路130的计数器140指定的地址中。当由停止条件检测电路100检测完成跟踪动作的条件时，传送信号120。停止信号由延迟电路150和先前指定的时间151延迟152。然后执行跟踪（状态历史存储）动作。以这种方式，跟踪后检测到停机条件，实现了一种易于高速诊断的设备进行诊断的工具。

70. 发明专利

JPS5727320A Operation panel 失效
标题翻译：操作面板
公开(公告)号：JPS5727320A
公开(公告)日：1982-02-13
申请号：JP10106980
申请日：1980-07-25
申请人： Toshiba Corp
发明人： ITAZU IKUYA
IPC分类号： G06F11/32 , G06F9/00 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To permit displaying of the contents of internal registers in order to analyze abnormality and faults by providing respectively specific mode switch, selector switch and display means. CONSTITUTION:A mode switch 2 assingning various kinds of operation modes including maintenance mode and a selector switch 1 assinging registers 6, 7 holding the information to be displayed in display elements 12 are provided to an operation panel provided with various switches for operating an electronic computer and the elements 12. Further, means 8-11 selecting one of the internal registers 6 for the purpose of maintenance through assignment of the maintenance mode by the switch 2 and assignment of the registers 6 by the switch 1 and displaying the contents held in this register 6 in the elements 12 are provided.
摘要翻译：目的：允许显示内部寄存器的内容，以分别提供特定模式开关，选择开关和显示装置来分析异常和故障。构成：将包含维护模式的各种操作模式的模式开关2和选择开关1分配到保持待显示在显示元件12中的信息的寄存器6,7被提供给具有用于操作电子计算机的各种开关的操作面板另外，装置8-11为了维护目的而选择一个内部寄存器6，通过由开关2分配维护模式和由开关1分配寄存器6，并且显示保存在其中的内容提供元件12中的寄存器6。

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