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1. 发明专利

JPS6438849A ADDRESS CONVERTER 失效
公开(公告)号：JPS6438849A
公开(公告)日：1989-02-09
申请号：JP19559687
申请日：1987-08-04
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/10 , G06F12/08
摘要： PURPOSE:To perform the address conversion of less overhead in parallel processings to increase the processing speed by loading an address conversion table shared among processors to one conversion buffer. CONSTITUTION:A conversion request and a virtual address from a processor B are set to a request flag 2 and a register 3 through lines 51 and 61, and the 8-bit output of request flags 1 and 2 and the register 3 is inputted to detecting circuits 20-23, and inputs from idle number registers 10-13 are checked, and only a circuit 21 outputs a coincidence detection signal 121 to a control circuit 6. Meanwhile, a page number output 101 from the register 3 is inputted to buffers 30-33. And outputs 130-133 of (set address)=8 are inputted to a selecting circuit 5 by the incorporated address conversion table, and the input 131 is selected by a select signal 140 from the circuit 6 and is outputted to a register 4. The actual page number and the actual address in the address conversion table are set to the register 4, and they are sent to a main storage device 7 together with an access request 150 through a line 160.

2. 发明专利

JPS63101966A VECTOR PROCESSOR 失效
公开(公告)号：JPS63101966A
公开(公告)日：1988-05-06
申请号：JP24718586
申请日：1986-10-17
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F17/16 , G06F15/78
摘要： PURPOSE:To improve processing performance by generating an interruption when the number of data to be processed by a vector instruction is smaller than a certain value. CONSTITUTION:An instruction, the kind of operation and an operand address are sent from an instruction control part 1 to a vector operating unit 2 through an interface signal line 120 and the number of data to be processed is sent to an output signal line 105 and set up in a vector length register 21. When the set value is smaller than the value of a reference vector length register 20, a mask flip flop 30 is reset. When an interruption enabled state is set up at that time, an AND condition is formed in an AND circuit 50 and informed to an interruption control circuit 3 through an output signal line 114 to start interruption sequence. When the number of data to be processed by the vector instruction is smaller than a certain value, the vector instruction is executed by generating an interruption to detect a part deteriorating the efficiency of execution and the detected part is substituted by a scalar instruction to improve the processing performance.

3. 发明专利

JPS62219044A MEMORY ACCESS CONTROLLER 失效
公开(公告)号：JPS62219044A
公开(公告)日：1987-09-26
申请号：JP6161986
申请日：1986-03-19
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/00 , G06F12/06
摘要： PURPOSE:To reduce queueing at a bank while securing the access order to improve the efficiency by deciding the priority level of access with position order information which determines the order of operation of request sources and access order information which determines the order in respective request sources of access to a memory. CONSTITUTION:Write requests on the memory are stored in buffers 11-14 of processing parts 1-4, and the first request of the processing part 1 is the access to an address A of the memory and a bank A is used. With respect to access, the first requests of processing parts 1-4 are processed in order and the second requests of them are performed in order, and requests are processed successively similarly. When the order of requests of processing parts 1-4 is indicated by values of read counters 21-24, namely, pointers 41-44, the 0th request in the processing part 1 of the write to the address A must be executed before that in the processing part of the write on the address A; but if the order of write requests on the same address is secured, it does not matter if these requests are processed equivalently or independently of the order of write requests on the other addresses.

4. 发明专利

JPS62174873A MEMORY ACCESS CONTROL SYSTEM 失效
公开(公告)号：JPS62174873A
公开(公告)日：1987-07-31
申请号：JP1631686
申请日：1986-01-28
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/06 , G06F12/00 , G06F17/16
摘要： PURPOSE:To attain a memory access with satisfactory rise of a calculation by processing an access in parallel, to both arrangement data from the time the bank competition does not occur when a succeeding arrangement data access is required during accessing the arrangement data. CONSTITUTION:When an element A6 is to be processed by a time T6 and the access request to succeeding arrangement data B is informed, a bank number 18 of a starting bank BO of the arrangement data B is set to a register 11. The interval information between elements of the arrangement data B is the same value as the interval information between elements of arrangement data A, and therefore, a bank number 12 of the arrangement data A is inputted into an access control circuit 20, a head bank number 18 of the arrangement data B is inputted, and from a bank cycle time, a bank width and a bank number during the access of the arrangement data A, the unable-to-start bank scope is calculated. As such a result, the unable-to-start scope comes to be the scope from before an N(Tc-1) bank until after a (N/2)(Tc+1) bank with a bank number 12 as a base point and after a time T7, the access of the arrangement data B can be executed alternately with the access of the arrangement data A.

5. 发明专利

JPS61173357A ADDRESS CONVERTING SYSTEM 失效
公开(公告)号：JPS61173357A
公开(公告)日：1986-08-05
申请号：JP1178685
申请日：1985-01-26
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/10
摘要： PURPOSE:To make the constitution of a system simple and to obtain an actual address all at once by converting simultaneously the address of plural continuous pages by a small quantity of hardware. CONSTITUTION:An address register 1 of an address converting system is divided into a partial space number S, the first and second page numbers M and N, and an address A in the page in the order from the higher order bit, a space selecting device 3 is controlled by the space number S, the contents of a control register 2 are selected and added to a space adjusting circuit 6 together with the numbers M and N. The number M is added directly and through an adder 5 to retrieving page change-over devices 10-13, and the number N is added through a page adjusting circuit 4 to change-over device 10-13. The address from the change-over devices 10-13 is processed by respective converting buffers of the converting sets 7 and 8, and added to an actual page change-over device 9. The change-over device 9 is controlled by the output of the circuit 6, and a page address is outputted all at once from respective actual page change-over devices 90-93.

6. 发明专利

JPS61173356A ADDRESS CONVERTING STSTEM 失效
公开(公告)号：JPS61173356A
公开(公告)日：1986-08-05
申请号：JP1178585
申请日：1985-01-26
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/10
摘要： PURPOSE:To reduce the quantity of the hardware and to convert the address of continuous several pages by obtaining simultaneously the actual page address for a continuous 2 to the Nth power of pages from the page designated by a logical address. CONSTITUTION:An address register 1 is respectively divided from an higher order bit into a partial space number S, the first page number M, the second page number N and an address A in the page, and the space number S is added through a control table 3 to a page adjusting circuit 6 together with the numbers M and N. The number M is added directly and through an adder 5 to a retrieving page change-over devices 10-13, and the number N is added through a page adjusting circuit 4 to change-over devices 10-13. The address from the change-over devices 10-13 is processed by a converting buffer of converting sets 7 and 8, and added to actual page change-over devices 90-93. The change- over devices 90-93 are controlled by the output of the circuit 6, and the actual address for continuous two pages designated by a little quantity of hardware is converted.

7. 发明专利

JPH01292533A PIPELINE CIRCUIT 失效
公开(公告)号：JPH01292533A
公开(公告)日：1989-11-24
申请号：JP12354888
申请日：1988-05-20
申请人： NEC CORP , KOFU NIPPON DENKI KK
发明人： FURUI TOSHIYUKI , ISHIZUKA TERU
IPC分类号： G06F9/38 , G06F12/06 , G06F17/16
摘要： PURPOSE:To attain the output of the valid data only even in case the data input timing is irregular or the valid and invalid states coexist by using the signal showing the valid or invalid state of the input data to control the production of the selection signal which decides the data holding time in a pipeline circuit. CONSTITUTION:A selection signal generating circuit 101 produces the selection signal to decide the data holding time of a data holding circuit 102. The circuit 101 is controlled by the input instruction signals T1-Tn which show the valid or invalid states of input signals A1-An respectively. When the signals T1-Tn show continuously the valid states, the selection signal holds the value of the data received first. While the selection signal is changed when a signal Tj showing an invalid state is received halfway. In such a way, only the valid data to be subsequently processed are delivered in the proper timing. Therefore both circuits 101 and 102 are set into a pipeline circuit 1000 which receives the input instruction signals T and A. Thus the valid data is delivered from a Z register 103.

8. 发明专利

JPS63221440A ADDRESS CONVERTING DEVICE 失效
公开(公告)号：JPS63221440A
公开(公告)日：1988-09-14
申请号：JP5734887
申请日：1987-03-11
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/10 , G06F12/08 , G06F17/16
摘要： PURPOSE:To reduce the overhead even in a multiple programming environment and to increase the arithmetic processing speed at the time of a vector arithmetic operation, by controlling an address conversion buffer based on a job number and a certain partial space unit. CONSTITUTION:The requester program number of a main memory access is held in a job number register 1 of an address converting device and a logic address is held in an address register 2. Then a real address obtained after conversion is held by an address register 3 and a pointer table for space switch instructions is held in a pointer register 6. A control circuit 5 a selection circuit 4, conversion buffers 30-33, and space number registers 10-13 are provided to those registers 1-3 and 6 respectively. Then the overall control is carried out under the control of the circuit 5 and the address conversion buffer is managed based on a job number and a certain partial space unit. Thus the overhead is reduced even under the multiple programming management and the vector arithmetic processing speed is increased.

9. 发明专利

JPS62264366A MEMORY ACCESS CONTROL SYSTEM 失效
公开(公告)号：JPS62264366A
公开(公告)日：1987-11-17
申请号：JP10909986
申请日：1986-05-13
申请人： NEC CORP
发明人： FURUI TOSHIYUKI
IPC分类号： G06F12/06 , G06F13/16 , G06F17/16
摘要： PURPOSE:To improve the leading characteristics of arithmetic with a small hardware quantity by processing accesses in parallel with each other to both arrays from a time point when no bank conflict occurs when an equal bank width at every machine cycle is obtained. CONSTITUTION:The start address of the 1st array data is set to a register 10 through an input signal line 100; while the start address of the 2nd array data is set to a register 11 via an input signal line 101 respectively. A register 12 maintains the interval between elements of an array. The outputs of both registers 10 and 11 selected by a selector 13 are added with the output of the register 12 via an adder 14 for the production of the next access address of each array. A comparator 21 compares the interval information on the array data under processing with that of the subsequent array data accesses and informs the coincidence of both interval information to an access control circuit 20. The circuit 20 transmits the request addresses on signal lines 110 and 111 to a memory so that no bank conflict occurs.

10. 发明专利

JPH03177958A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH03177958A
公开(公告)日：1991-08-01
申请号：JP31715989
申请日：1989-12-06
申请人： NEC CORP , KOFU NIPPON DENKI KK
发明人： FURUI TOSHIYUKI , TAKEGAWA SHIGENORI
IPC分类号： G06F15/16 , G06F12/06 , G06F13/18 , G06F15/167
摘要： PURPOSE:To prevent interfacing concentrated on one memory device occurring and to facilitate handling on a program by separating the memory device to local storage dedicated for each group and shared storage accessible from two groups. CONSTITUTION:Six processors PA1 - PC2 are separated to groups A - C by every two sets, and are connected to system controllers SA - SC provided corre sponding to the groups, and make access local memory devices LMA - LMC dedicated for each of the groups A - C, and perform data processing jointly or independently. Shared memory devices CMAB, CMBC, and CMCA accessible from four processors of both groups, respectively are connected between each of the system controllers SASC. Thereby, since it is possible to handle all the shared storage and local storage connected to one group on the same address space, the concentration of interfacing on one memory device can be prevented occurring, and the handling on the program can be facilitated.

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