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61. 发明专利

JPH01246825A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01246825A
公开(公告)日：1989-10-02
申请号：JP7330388
申请日：1988-03-29
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/265 , H01L21/28
摘要： PURPOSE:To satisfy the ohmic characteristics between a P-type diffusion layer and a silicide layer and the bonding characteristics of a substrate by a method wherein, P-type impurities are ion-implanted after a process to form a P-type impurity layer on a silicon substrate and a process forming silicide have been finished. CONSTITUTION:After boron has been implanted through the thermally oxides film 2 of 100Angstrom formed on an N-type silicon substrate 1, a P-type impurity layer 3 of 0.3mum in depth is formed by conducting an annealing work in an N2 atmosphere. Then, the film 2 is removed, titanium of 800Angstrom is deposited using a sputtering method, annealing and etching treatments are conducted, and a titanium-silicide layer 4 of 1000Angstrom is formed. The specific resistance of this layer can be lowered to about 20muOMEGAcm, and as a P-type diffusion layer of 0.2mum is located under said layer, there is no problem pertaining to the leakage in bonding. Then, by ion-implanting boron, the density in the vicinity of the interface of a P-type diffusion layer 5 is increased, and excellent ohmic characteristics between the P-type diffusion layer and the silicide layer 4 can be obtained.

62. 发明专利

JPS6376335A FORMATION OF INSULATING FILM OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6376335A
公开(公告)日：1988-04-06
申请号：JP21801486
申请日：1986-09-18
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/316
摘要： PURPOSE:To make it possible to form a high-quality insulating film in such a way that, after liquid glass has been spin-coated, a microwave generated with a magnetron is radiated. CONSTITUTION:After a device layer 2 has been formed on a semiconductor substrate 1 and a metal wiring part 3 has been formed, liquid glass 4 is spin- coated. An organic solvent 5, an OH group and the like are contained in the liquid glass 4. After that, if the assembly is heated at 300-450 deg.C, the organic solvent 5 is completely evaporated, but a small amount of the OH group remains. If a microwave 7 is radiated in this state, the OH group 6 is resonated and is heated by a molecular movement. Then, the OH group reacts with other OH groups and is then transformed into a vapor which is then expelled from the surface of a semiconductor. As a result, a high-quality insulating film without containing the OH group can be deposited.

63. 发明专利

JPS58213450A Structure of multilayer wiring of semiconductor device 失效
标题翻译：半导体器件多层布线结构
公开(公告)号：JPS58213450A
公开(公告)日：1983-12-12
申请号：JP9603282
申请日：1982-06-04
申请人： Toshiba Corp
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To prevent breaking at stages, the increase of resistance, etc. of a wiring layer by dividing a connecting hole into plural numbers and passing one part of the wiring layer through a region in which there is no stepped difference. CONSTITUTION:The four connecting small holes 8a, 8b, 8c, 8d are arranged and formed to a first insulating film 3 on a straight line along the longitudinal direction of a second wiring layer 5. Consequently, one part of the third wiring layer 7 can be passed through the region in which there is no stepped difference. The third wiring layer 7 crosses stepped difference in a section B-B by the arrows. Accordingly, the disconnection and increase of resistance of the third wiring layer 7 resulting from breaking at stepped difference sections the decrease of film thickness, etc. can be prevented.
摘要翻译：目的：通过将连接孔分割成多个数量并使布线层的一部分通过没有阶梯差的区域，来防止在阶段中的断开，布线层的电阻等的增加。构成：四个连接小孔8a，8b，8c，8d沿着第二布线层5的长度方向在直线上布置并形成在第一绝缘膜3上。因此，第三布线层7的一部分通过没有阶差的区域。第三布线层7通过箭头跨越B-B部分的台阶差。因此，可以防止由阶梯差分部分断裂导致的第三布线层7的电阻的断开和增加，从而降低膜厚度等。

64. 发明专利

JPS57121269A Substrate bias generating circuit 失效
标题翻译：基板偏压发生电路
公开(公告)号：JPS57121269A
公开(公告)日：1982-07-28
申请号：JP668981
申请日：1981-01-20
申请人： Toshiba Corp
发明人： USHIKU YUKIHIRO
IPC分类号： H01L27/04 , G05F3/20 , G11C11/408 , H01L21/822 , H03K19/094
CPC分类号： G05F3/205
摘要： PURPOSE:To stably control the bias voltage of a substrate independently from other MOS semiconductor circuit by controlling the operation of a substrate bias generator in a substrate potential detector operated with a bias voltage as a reference level. CONSTITUTION:The output of a reference bias generator 1 is inputted to a substrate potential detector 3 having an FET in an input stage. The detector 3 has a depletion type FET Q1 as a load and enhancement type FETs Q2, Q3, Q4 to from a Schmitt trigger circuit, thereby operating in Schmitt circuit with a substrate bias potential fed back to the source of the FET Q3 and the ground potential (reference potential) applied to its gate. In this case, the source potential of the FET Q3 is set to the bias voltage of the substrate. In this manner, the detector 3 compares the substrate bias voltage fed back with the ground potential as the reference voltage, with the result that it control in ON or OFF the operation of the substrate bias generator 1.
摘要翻译：目的：通过控制以偏置电压作为参考电平运行的衬底电位检测器中的衬底偏置发生器的操作，来稳定地控制衬底的偏置电压与其它MOS半导体电路独立。构成：参考偏置发生器1的输出被输入到具有输入级中的FET的衬底电位检测器3。检测器3具有作为来自施密特触发电路的负载和增强型FET Q2，Q3，Q4的耗尽型FET Q1，从而在具有反馈到FET Q3和地的源极的衬底偏置电位的施密特电路中操作电位（参考电位）施加到其门。在这种情况下，FET Q3的源极电位被设定为衬底的偏置电压。以这种方式，检测器3将反馈的衬底偏置电压与接地电位作为参考电压进行比较，结果是它控制在衬底偏置发生器1的操作中的ON或OFF。

65. 发明专利

JP2007300144A Inspection method for semiconductor wafer, developing method of semiconductor device, and semiconductor wafer processing apparatus 有权
标题翻译：半导体器件的检测方法，半导体器件的开发方法和半导体器件加工设备
公开(公告)号：JP2007300144A
公开(公告)日：2007-11-15
申请号：JP2007211031
申请日：2007-08-13
申请人： Toshiba Corp , 株式会社東芝
发明人： KANGEN JUNJI , TANZAWA KATSUJIRO , TSUCHIYA NORIHIKO , USHIKU YUKIHIRO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To quantitatively evaluate crystal defects over the whole surface of a wafer, after device formation.
SOLUTION: A method for inspecting a semiconductor wafer which has a film to form a device structure including a device pattern and has a crystal defect in some cases, comprises a process of exposing the crystal surface of the semiconductor wafer, by removing the device structure film with a chemical solution, a process of making apparent any crystal defects by selectively removing the surface layer of the semiconductor wafer through selective etching, and a process of quantitatively evaluating the crystal defects.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：待解决的问题：在器件形成之后，定量评估晶片的整个表面上的晶体缺陷。解决方案：一种用于检查具有膜以形成包括器件图案并且在某些情况下具有晶体缺陷的器件结构的半导体晶片的方法包括通过将半导体晶片的晶体表面曝光具有化学溶液的器件结构膜，通过选择性蚀刻选择性去除半导体晶片的表面层而产生任何晶体缺陷的过程，以及定量评价晶体缺陷的过程。版权所有（C）2008，JPO＆INPIT

66. 发明专利

JP2007059945A Manufacturing equipment of semiconductor device, control method of manufacturing method of semiconductor device, control equipment of manufacturing equipment of semiconductor device, simulation method and simulation device 有权
标题翻译：半导体器件的制造设备，半导体器件的制造方法的控制方法，半导体器件的制造设备的控制设备，模拟方法和仿真器件
公开(公告)号：JP2007059945A
公开(公告)日：2007-03-08
申请号：JP2006307235
申请日：2006-11-13
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , NAKAMURA MITSUTOSHI
IPC分类号： H01L21/31 , C23C16/52
摘要： PROBLEM TO BE SOLVED: To provide manufacturing equipment of a semiconductor device which is capable of performing a semiconductor manufacturing process using thermal reaction while maintaining appropriate condition irrespective of the condition of atmosphere. SOLUTION: In a plurality of pipes 78a-78d provided in the manufacturing equipment 61 of the semiconductor device, a predetermined process of manufacturing the semiconductor device using thermal reaction is performed, and several types of gases are fed to be introduced into a treatment part 4 in which operating state and the like are controlled by a process treatment part control equipment 2. A process control equipment 62 has a piping information processing part 68 which performs a logical operation processing for adjusting type and flow rate of each gas which passes through each of pipes 78a-78d, and an introductory gas selection information data storage part 69 which stores the logical information which the processing part 68 processed. The process control equipment 62 measures at least one of the flow rate and the temperature of the gas in the treatment part 4 at a predetermined time interval while the process is performed, and stops the process when an analysis value, which is analyzed based on a measured value and the logical information of the storing part 69, reaches a predetermined value. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件的制造设备，该半导体器件能够在保持适当条件的同时进行使用热反应的半导体制造工艺，而与大气条件无关。解决方案：在设置在半导体器件的制造设备61中的多个管78a-78d中，执行使用热反应制造半导体器件的预定工艺，并且将几种类型的气体馈送到处理部4，其中通过处理处理部控制装置2控制操作状态等。过程控制设备62具有管道信息处理部分68，其执行用于调节通过的每种气体的类型和流量的逻辑运算处理通过管道78a-78d中的每一个以及存储处理部分68所处理的逻辑信息的介绍性气体选择信息数据存储部分69。过程控制设备62在处理过程中以预定的时间间隔测量处理部分4中的气体的流量和温度中的至少一个，并且当基于测量值和存储部分69的逻辑信息达到预定值。版权所有（C）2007，JPO＆INPIT

67. 发明专利

JP2006293433A Quality control system, quality control method, and wafer processing method in lot unit 有权
标题翻译：质量控制系统，质量控制方法和大部分的加工方法
公开(公告)号：JP2006293433A
公开(公告)日：2006-10-26
申请号：JP2005109209
申请日：2005-04-05
申请人： Toshiba Corp , 株式会社東芝
发明人： OGAWA AKIRA , USHIKU YUKIHIRO , INO TOMOMI
IPC分类号： G05B19/418 , G01M99/00 , H01L21/02
CPC分类号： G05B19/41875 , G05B2219/32097 , G05B2219/32194 , G05B2219/45031 , H01L21/67253 , Y02P90/20 , Y02P90/22
摘要： PROBLEM TO BE SOLVED: To provide a quality control system which reduces the possibility of missing defective lots. SOLUTION: The quality control system is provided with a QC value storage 22 which stores QC values of lots actually measured in the past; a data acquisition device 3 which acquires device-internal information on a processing device 10 processing an object lot; a device-internal information storage 21 which stores the device-internal information; a recipe storage 24 which stores a plurality of recipes classified according to a sampling density distribution in a wafer; a QC value estimation means 11 which estimates a QC estimation value of an object lot, based on the device-internal information and the QC values of lots which are actually measured in the past; a wafer determination means 12 which determines a sample wafer to be measured among a plurality of wafers constituting the object lot, based on the estimated QC values; a recipe selection means 13 which selects an adaptable recipe to be adapted to the sample wafer from the plurality of recipes based on the estimated QC values; and a measuring device 4 which conducts QC measurement to the sample wafer, by using the adaptable recipe and stores the result of the measurement in the QC value storage 22. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少缺陷批次的可能性的质量控制系统。
解决方案：质量控制系统设置有QC值存储器22，其存储过去实际测量的批次的QC值; 数据获取装置3，其在处理对象批次的处理装置10上获取装置内部信息; 存储设备内部信息的设备内部信息存储器21; 存储根据晶片中的采样密度分布分类的多个配方的配方存储器24; 基于过去实际测量的装置内部信息和批次的QC值来估计对象批次的QC估计值的QC值估计装置11; 晶片确定装置12，其基于估计的QC值确定构成对象批次的多个晶片中的待测量样品晶片; 配方选择装置13，其基于估计的QC值从多个配方中选择适合于样本晶片的适应性配方; 以及测量装置4，其通过使用适应性配方向样品晶片进行QC测量，并将测量结果存储在QC值存储器22中。（C）2007，JPO和INPIT

68. 发明专利

JP2006196926A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006196926A
公开(公告)日：2006-07-27
申请号：JP2006108912
申请日：2006-04-11
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , MIZUNO TOMOHISA , YOSHIMI MAKOTO , TERAUCHI MAMORU , KAWANAKA SHIGERU
IPC分类号： H01L29/78 , H01L29/41
CPC分类号： H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which element characteristics can be improved. SOLUTION: The semiconductor device includes: a substrate 21 having a projecting semiconductor element region 23; a gate electrode formed on the upper and lateral surfaces of the element region 23; an insulating film 41 for covering the element region 23 and provided with a contact hole; and first and second contact wirings 43 for embedding a contact hole and coming in contact with the element region 23. In the element region 23, a source region 47 and a drain region 48 are spaced apart each other and come in contact with the first and the second contact wirings 43, respectively; at least one contact wiring 43 comes in contact with both a part of the upper surface and a part of the lateral surfaces of the element region 23; and the thickness of the source region 47 or the drain region 48 coming in contact with the contact wiring 43 is thicker at a position coming in contact with the contact wiring 43, as compared with a position not coming in contact with the contact wiring 43. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高元件特性的半导体器件。解决方案：半导体器件包括：具有突出的半导体元件区域23的衬底21; 形成在元件区域23的上表面和侧表面上的栅电极; 用于覆盖元件区域23并设置有接触孔的绝缘膜41; 以及用于嵌入接触孔并与元件区域23接触的第一和第二接触布线43.在元件区域23中，源极区域47和漏极区域48彼此间隔开并与第一和第二接触布线接触第二接触线43; 至少一个接触配线43与元件区域23的上表面的一部分和侧面的一部分接触; 与不与接触配线43接触的位置，与接触配线43接触的位置处，与接触配线43接触的源极区域47或漏极区域48的厚度较厚。版权所有（C）2006，JPO＆NCIPI

69. 发明专利

JP2005294382A Semiconductor wafer and manufacturing method thereof 审中-公开
标题翻译：半导体晶圆及其制造方法
公开(公告)号：JP2005294382A
公开(公告)日：2005-10-20
申请号：JP2004104653
申请日：2004-03-31
申请人： Toshiba Corp , 株式会社東芝
发明人： YANAGIYA NARUTOSHI , USHIKU YUKIHIRO
IPC分类号： H01L21/66 , H01L21/76 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor wafer which can evaluate with excellent sensitivity the difference in the rates of crystal defect generated in a semiconductor substrate resulting from shape of evaluation pattern. SOLUTION: The semiconductor wafer is formed with aggregation of a plurality of striped diffusing regions 111, 112, 113, 121, 122, 123, 131, 132, and 133 which are formed in an element isolation insulating film 15 at the surface of a semiconductor substrate 1 and includes a plurality of evaluation patterns 101, 102, and 103 for detecting a joining leak current at the diffusing regions 111, 112, 113, 121, 122, 123, 131, 132, and 133. Widths W 11i , W 12i , and W 13i of the element isolation insulating film 15 surrounded by a plurality of diffusing regions 111, 112, 113, 121, 122, 123, 131, 132 and 133 in a plurality of respective aggregations are different for each of a plurality of evaluation patterns 101, 102, and 103. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体晶片，其可以以极好的灵敏度评估由评估图案的形状导致的在半导体衬底中产生的晶体缺陷的差异。解决方案：半导体晶片形成有多个条纹漫射区域111,112,113,121,122,123,131,132和133的聚集，所述多个条纹漫射区域111,112,113,121,122,123,131,132和133形成在元件隔离绝缘膜15的表面并且包括用于检测扩散区域111,112,113,121,122,123,131,132和133处的接合泄漏电流的多个评估图案101,102和103。宽度W < 由多个扩散区域111,112,113,121,121包围的元件隔离绝缘膜15的SB> 11i ，W 和W SB 13i 多个评估图案101,102和103中的每一个的多个相应聚集中的122,123,131,132和133是不同的。（C）2006，JPO和NCIPI

70. 发明专利

JP2005276915A Process management system and method 有权
标题翻译：过程管理系统和方法
公开(公告)号：JP2005276915A
公开(公告)日：2005-10-06
申请号：JP2004084682
申请日：2004-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUCHIYA NORIHIKO , USHIKU YUKIHIRO
IPC分类号： H01L27/108 , H01L21/00 , H01L21/02 , H01L21/66 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/78
CPC分类号： H01L21/67253 , H01L22/20 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a process management system capable of improving processes causing generation of dislocation. SOLUTION: The process management system comprises a section 2 for acquiring an inspection dislocation image in a semiconductor device fabricated in a semiconductor substrate; a section 4 for acquiring process conditions each of a plurality of processes fabricated the semiconductor device; a section 8 for acquiring the structure of a semiconductor substrate being processed in an object process, set among the plurality of processes; a stress-analyzing section 10 for calculating stress at a plurality of nodes set in the structure, based on the process conditions and the structure; a section 12 for setting a plurality of starting points at such positions as stress concentration exceeding a reference level is predicted; a dislocation dynamics analyzing section 14 for predicting formulation of analysis dislocation line, by calculating dislocation growth process in the stress field for each of the plurality of starting positions; and a section 16 for deciding whether the object process is a process possibly causing generation of dislocation, by comparing the formulation of analysis dislocation line with the inspection dislocation image. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够改善引起错位产生的过程的过程管理系统。解决方案：过程管理系统包括用于在制造在半导体衬底中的半导体器件中获取检查位错图像的部分2; 用于获取制造半导体器件的多个工艺中的每个处理条件的部分4; 在多个处理中设置用于获取在对象处理中处理的半导体衬底的结构的部分8; 应力分析部10，用于根据处理条件和结构计算结构中设定的多个节点的应力; 预测用于在诸如应力集中超过参考水平的位置设置多个起点的部分12; 位错动力学分析部分14，用于通过计算多个起始位置中的每一个的应力场中的位错生长过程来预测分析位错线的公式; 以及用于通过将分析位错线的配方与检查位错图像进行比较来判定对象处理是否是可能引起错位产生的部分16。版权所有（C）2006，JPO＆NCIPI

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