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61. 发明专利

JPS589458B2 失效
公开(公告)号：JPS589458B2
公开(公告)日：1983-02-21
申请号：JP7827278
申请日：1978-06-28
申请人： FUJITSU LTD
发明人： TAKABA KINZO , TSUBOI HIDEO , YAMAMOTO HIROYUKI , NAGANO YOSHIHIRO
IPC分类号： G06F15/16 , G06F1/04 , G06F1/14 , G06F15/177

62. 发明专利

JPS55127749A TRANSMISSION CONTROL CIRCUIT 失效
公开(公告)号：JPS55127749A
公开(公告)日：1980-10-02
申请号：JP3527879
申请日：1979-03-26
申请人： FUJITSU LTD
发明人： IMAI TADAAKI , YAMAMOTO HIROYUKI , KOBAYASHI MASAAKI , AZUMA MASAYUKI
IPC分类号： H04L5/16 , G06F13/00 , H04L25/45 , H04L29/02 , H04L29/06
摘要： PURPOSE:To make half-duplex communication possible by providing a circuit which performs inter-frame time fill IFTF of a flag pattern under the idle state and performs IFTF of the pattern of all marks in case that transmission abandonment is dispalyed. CONSTITUTION:After stored in data register 11, write data WD from LA (line adapter) bus is transferred to P/S serial.parallel register 12 under the parallel state. Register adds flag F, etc., to input data and transmits it under the serial state. If the FF in control circuit is ''0'', flag generator 15' is operated, and the flag is supplied to register 12 to obtain a pattern with flag F inserted to inter-frame IFT. If the FF is ''1'' under the idle state, mark generator 15 is selected, and signals 1, 1...1 are transmitted from mark generator 15 to line 14 through gate 13. Control circuit 10 is controlled by register address RA.

63. 发明专利

JPS55124841A DATA RECEPTION CONTROL UNIT 失效
公开(公告)号：JPS55124841A
公开(公告)日：1980-09-26
申请号：JP3299179
申请日：1979-03-20
申请人： FUJITSU LTD
发明人： IMAI TADAAKI , YAMAMOTO HIROYUKI , KOBAYASHI MASAAKI , AZUMA MASAYUKI
IPC分类号： H04L29/02 , G06F13/00 , H04L13/00
摘要： PURPOSE:To make easy the control including CRC register and to avoid unnecessary interruption, to bit serial for the data transfer between the reception registers, by providing four reception registers of 1 byte capacity possible for transmission control in HDLC (High level Data Link Control). CONSTITUTION:The data in HDLC step is written in the reception register 31 via the 0 delete circuit 37, and write-in to the reception register 32 of the reception data is made at the register control 39 when flag F is detected at the flag detection circuit, and 8-bit data is transferred to the registers 33-36 in bit serial after that. The counter 42 performs count every 1 byte and the count value of 4 is reached, then the reception of minimum frame constitution is confirmed to inform it to program and request read-in, and if no minimum frame constitution is given, no read- in request is made. In parallel with the shift operation, error check by CRC register 40 is made and the result is informed to the program.

64. 发明专利

JPS5587273A CASH REGISTER 失效
公开(公告)号：JPS5587273A
公开(公告)日：1980-07-01
申请号：JP15914378
申请日：1978-12-26
申请人： FUJITSU LTD
发明人： HAMANO YUTAKA , MATSUMOTO TSUTOMU , TANAKA TOSHIYUKI , YAMAMOTO HIROYUKI , KUROKI AKIRA , SUZUKI AKIRA , UETAKE MITSUO
摘要： PURPOSE:To prevent an error from occurring by verifying the total numbers of sheets by kinds of money and kinds of bonds by comparing the total numbers of sheets by kinds of money and kinds of bonds calculated from the numbers of sheets by kinds of money and kinds of bonds with the newly-recounted numbers of sheets, and then by providing error display when the both disagree each other. CONSTITUTION:Input data are stored in register group 4. Among register group 4, the numbers of sheets of money by kinds of money are stored in registers 41-44, and the amount of money is in register 45; and the numbers of sheets by kinds of bonds are registered in registers 46 and 48, the amounts of bonds are stored in registers 47 and 49, and payment and receipt amounts on a slip are stored in register 50. To the itemized numbers of sheet and amounts stored, the number of sheets and amount inputted from input registers 53 and 54 are added by using adder group 7 and results are stored in register group 4 again. Data stored are used to calculate the total number of sheets, that of bonds, and the total amounts by kinds of operators 81-83, and results are compared with values of input registers 51 and 52, and register 50; when they are disagree mutually, error display is provided by display unit 88.

65. 发明专利

JPS5587269A CASH REGISTER 失效
公开(公告)号：JPS5587269A
公开(公告)日：1980-07-01
申请号：JP15912878
申请日：1978-12-26
申请人： FUJITSU LTD
发明人： OKUYAMA RIYOUICHI , NAGANO YOSHIHIRO , TSUBOI HIDEO , YAMAMOTO HIROYUKI
摘要： PURPOSE:To reduce the possibility of the occurrence of an error by deciding on whether the result of subtraction of a subtrahend from a minuend of every process is positive or negative, and then by displaying it on part of a data display part. CONSTITUTION:Data having passed through main task 32 are stored in item buffer memory 36 and then transferred to data display part 13 by way of control part 35, main task part 32, and control parts 37 and 42 to display respective items in corresponding areas. Every time data is inputted, counter arithmetic part 33 updates corresponding data by adding or subtracting. With an end key depressed, count arithmetic program control part 33-2 calculates a difference amount between an input amount stored in counter memory 34 and itemized data. When the difference amount is zero, the contents of memory 34 are transferred to a center by processing part 43 via transmission control part 38.

66. 发明专利

JPS554676A TIMER CONTROL SYSTEM FOR DATA PROCESS SYSTEM 失效
公开(公告)号：JPS554676A
公开(公告)日：1980-01-14
申请号：JP7827278
申请日：1978-06-28
申请人： FUJITSU LTD
发明人： TAKABA KINZOU , TSUBOI HIDEO , YAMAMOTO HIROYUKI , NAGANO YOSHIHIRO
IPC分类号： G06F15/16 , G06F1/04 , G06F1/14 , G06F15/177
摘要： PURPOSE:To save the memory capacity necessary for the timer subroutine with no waste through sharing of the timer subroutine by plural microprocessors. CONSTITUTION:Microprocessors A and B possess control memories CM1 and CM2 as the prescribed process means plus order execution units PU1 and PU2 as the process units, and the transfer is given to the next process step in case the fixed time elapses from a fixed time. In such data process system, jump address table 9 to store the order of the timer subroutine plus input/output boats IP1 and IP5 are provided to processor A, and input/output boats IP2, IP4 and IP5, timer table memory 12 plus clock generator 13 are provided to processor B respectively. Thus, the timer subroutine can be shared, decreasing the memory capacity necessary for the timer subroutine.

67. 发明专利

JPS54148511A Data reproducing system 失效
标题翻译：数据复制系统
公开(公告)号：JPS54148511A
公开(公告)日：1979-11-20
申请号：JP5651678
申请日：1978-05-15
申请人： Fujitsu Ltd
发明人： HAMANO YUTAKA , NAGANO YOSHIHIRO , TSUBOI HIDEO , YAMAMOTO HIROYUKI , MORIYA KAZUMASA , NAGAI TADAICHIROU
IPC分类号： G11B20/18 , G11B5/09
摘要： PURPOSE: To perform reading strong to jitter and skew by independently reading out the logics 0, 1 of the digital data having been recorded in two sets of tracks and combining the read-out signals from the respective tracks according to the presence or not of the change in polarity data.
CONSTITUTION: The logics 0, 1 of the digital signal D have respectively separately been recorded in the zero track 11 and 1 track 12 of a magnetic tape 10. These records are separately reproduced by a magnetic head, whereby the reading strong to jitter is accomplished. The presence or not of the change in the polarities of the reproduction signal in the search signal periods T
1 , T
2 ... of about one and half times the inter bit spacing is detected at this reading. If the outputs are so combined that, when there is no change in the polarity at each bit, the read-out signal of the track 12 is outputted for the track 11 and when there is a change in the polarity at each bit, the read-out signal of the track 11 is outputted for the track 12, whereby reading strong even to jitters may be accomplished.
COPYRIGHT: (C)1979,JPO&Japio
摘要翻译：目的：通过独立地读出已经记录在两组轨道中的数字数据的逻辑0，将抖动和倾斜强度进行读取，并根据不同的轨迹是否存在来自各个轨道的读出信号改变极性数据。构成：数字信号D的逻辑0,1分别分别记录在磁带10的零磁道11和1磁道12中。这些记录由磁头单独再现，从而完成对抖动的读数。在该读数时检测在搜索信号周期T1，T2 ...中的位数间隔的大约一倍和两倍的再现信号极性的变化的存在与否。如果输出如此组合，当每个位的极性没有变化时，轨道12的读出信号被输出到轨道11，并且当每个位的极性发生变化时，读出输出磁道11的轨道11的输出信号，从而可以实现强烈甚至抖动的读取。

68. 发明专利

JPS548488A SEMICONDUCTOR PHOTO DETECTOR 失效
公开(公告)号：JPS548488A
公开(公告)日：1979-01-22
申请号：JP7421377
申请日：1977-06-22
申请人： FUJITSU LTD
发明人： SUYAMA KATSUHIKO , YAMAMOTO HIROYUKI
IPC分类号： H01L29/80 , H01L27/095 , H01L29/76 , H01L31/10
摘要： PURPOSE:To easily form the high resistance parallely connected between the gate and source of the photo detector, by extending the source and the drain electrode formed on the conductive layer up to the buffer layer exposed under the conductive layer, and by taking the buffer layer between the extended electrodes as a resistor.

69. 发明专利

JPS5383445A TERMINAL UNIT CONTAINING CARD READER TEST FUNCTION 失效
公开(公告)号：JPS5383445A
公开(公告)日：1978-07-22
申请号：JP14681276
申请日：1976-12-07
申请人： FUJITSU LTD
发明人： AIZAKI YOSHIHIKO , YAMAMOTO HIROYUKI
IPC分类号： G06K7/00 , G06Q20/40 , G06Q40/00 , G06Q40/02
摘要： PURPOSE:To achieve a terminal unit containing the magnetic card reader test function which avoids the display of the magnetic card's secret number of a specified king, by providing both the identification code decision part and the secret number cutting part. Thus, the crime-prevention efficiency can be cnhanced.

70. 发明专利

JP2012060247A Cellphone device, cellphone control method and cellphone control program 有权
标题翻译：电话设备，电话控制方法和电话控制程序
公开(公告)号：JP2012060247A
公开(公告)日：2012-03-22
申请号：JP2010199058
申请日：2010-09-06
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KIMURA TOMONORI , KONNO HIDENORI , YAMAMOTO HIROYUKI
IPC分类号： H04W48/02 , H04W84/10
摘要： PROBLEM TO BE SOLVED: To provide a cellphone device that increases security by limiting the range of connection to a WLAN network to a range narrower than the WLAN network.SOLUTION: A WLAN communication control section 13 connects to a WLAN base station to establish communication using a WLAN network. A femto communication control section 12 connects to a femto base station having a narrower communication range than the WLAN base station to establish communication using a femto network. A communication limitation section 111 instructs the WLAN communication control section 13 to connect to a predetermined WLAN base station if communication can be established with a predetermined femto base station having a communication range partly or wholly included in the communication range of the predetermined WLAN base station.
摘要翻译：要解决的问题：提供通过将WLAN网络的连接范围限制在比WLAN网络窄的范围来增加安全性的蜂窝电话设备。解决方案：WLAN通信控制部分13连接到WLAN基站，以使用WLAN网络建立通信。毫微微通信控制部分12连接到具有比WLAN基站更窄的通信范围的毫微微基站，以使用毫微微网络建立通信。通信限制部分111指示WLAN通信控制部分13连接到预定的WLAN基站，如果可以与具有部分或全部包含在预定WLAN基站的通信范围内的通信范围的预定毫微微基站建立通信。版权所有（C）2012，JPO＆INPIT

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