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61. 发明专利

JPH11261228A MULTILAYERED PRINTED WIRING BOARD 失效
公开(公告)号：JPH11261228A
公开(公告)日：1999-09-24
申请号：JP8253798
申请日：1998-03-13
申请人： IBIDEN CO LTD
发明人： ASAI MOTOO , SEGAWA HIROSHI , NODA KOTA , KARIYA TAKASHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayered printed wiring board which has small dimensional changes in the X-Y and Z directions and less surface waviness and warping. SOLUTION: In a multilayered printed wiring board formed by alternately laminating interlayer resin insulating layers 50 and conductor layers 58 upon another on a core substrate 30, the core substrate 30 is formed by laminating six or more layers of prepreg 20 obtained by impregnating cloth, such as the glass cloth, etc., made of fibers having low thermal expansion with a bis(maleimide)triazine resin and having a thickness of

62. 发明专利

JPH11233950A MANUFACTURE OF MULTILAYER PRINTED WIRING BOARD 失效
公开(公告)号：JPH11233950A
公开(公告)日：1999-08-27
申请号：JP28590898
申请日：1998-09-21
申请人： IBIDEN CO LTD
发明人： HIRAMATSU YASUJI , ASAI MOTOO , HIROSE NAOHIRO , KARIYA TAKASHI
IPC分类号： B23K26/00 , B23K26/02 , B23K26/08 , B23K26/382 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing multilayer printed wiring board with which many via holes can be opened with a laser beam by securing the accuracy of the opening positions of the holes, without relaying upon the accuracy of the projecting position of the laser beam. SOLUTION: After a CU film 30 which becomes a conformal mask is provided on a substrate 20, and openings 30a for forming via holes and positioning marks 30b are formed on the Cu film 30, the position of the substrate 20 is measured by measuring the positions of the marks 30b with a camera 82 and openings for forming via holes are formed at or near the positions of the openings 30a by having the openings 30a irradiated with a laser beam. Since the accuracy of the opening positions of the via holes varies depending on the positional accuracy of the openings 30a, the via holes can be formed at appropriate positions even if the accuracy of the projecting position of the laser beam is low.

63. 发明专利

JPH11121926A MULTILAYER PRINTED WIRING BOARD AND ITS MANUFACTURE 失效
公开(公告)号：JPH11121926A
公开(公告)日：1999-04-30
申请号：JP28050197
申请日：1997-10-14
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI , ASAI MOTOO , SHIMADA KENICHI , SEGAWA HIROSHI
IPC分类号： H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To secure the adhesion property with a conductor circuit and to improve reliability even when a high melt-point resin such as fluororesin is adopted for a substrate and an interlayer insulation material, by forming an alloy roughened layer on the surface of the conductor circuit. SOLUTION: A copper-clad laminate where a copper foil 2 being roughed on one surface is laminated is used for both surfaces of a substrate where fluororesin is impregnated into a glass cloth, the pattern of an etching resist 3 is formed on one surface at a side where conductor circuit is formed and is etched, and then the etching resist 3 is peeled and removed, thus forming a conductor circuit 4. Then, electroless plating is made and a roughened layer 6 of Cu-Ni-P alloy is provided on the surface of the conductor circuit 4, thus obtaining a circuit substrate. As a result, even when a high melt-point resin such as fluororesin is adopted for a substrate or an interlayer insulation material, adhesion property as the conductor circuit is secured, thus obtaining a multilayer printed wiring board with improved reliability.

64. 发明专利

JPH09219485A MANUFACTURE OF SUBSTRATE FOR LOADING ELECTRONIC COMPONENT 失效
公开(公告)号：JPH09219485A
公开(公告)日：1997-08-19
申请号：JP5098396
申请日：1996-02-13
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： H01L23/50
摘要： PROBLEM TO BE SOLVED: To provide the manufacture of a substrate, in which a bent stepped section is bent and formed accurately to a lead and the deformation of a frame section for fixing the lead can be inhibited and which is used for loading an electronic component. SOLUTION: When bent stepped sections 12 are formed to a large number of leads 10, in which joining end sections 11 are joined around a substrate 2, the joining end sections 11 of the leads 10 are connected to the lands 22 of through-holes 20 shaped to the substrate 2. The leading-out sections 13 of the leads are arranged between the plane section 310 of a top force 31 and the plane section 320 of a bottom force 32. Pushing load is applied to the substrate 2 by a punch 30, the leads 10 are deformed along the side face of the substrate 2, and the bent stepped sections 12 are formed. It is preferable that the above-mentioned pushing load is applied under the state, in which a reinforcing resin is bonded and covered so as to cover the surfaces of the joining end sections 11.

65. 发明专利

JPH08274217A WIRING BOARD FOR MOUNTING ELECTRONIC COMPONENTS 失效
公开(公告)号：JPH08274217A
公开(公告)日：1996-10-18
申请号：JP9964595
申请日：1995-03-30
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： H01L23/12 , H05K3/34 , H05K3/42
摘要： PURPOSE: To provide a wiring board for mounting electronic components wherein the arrangement region of through holes capable of solder supply is wide and the freedom of wiring board design is large. CONSTITUTION: The title wiring board is provided with the following; a conductor pattern 11 formed on at least one surface, a plurality of through holes 12, penetrating hoes 13 which are formed in specific positions and accommodate electronic components, an upper and lower conduction part 14 having an inner peripheral surface plating part 141 formed by plating the inner peripheral surfaces of the through holes and a pair of auxiliary electrode part 142 formed on the aperture edge parts of the through holes, and a plurality of lead frames 15 to be electrically connected with the upper and lower conduction part 14 by using solder. Out of a pair of the auxiliary electrode parts 142A, 142B, at least a part of a plurality of the solder introducing side auxiliary electrode parts 142B positioned on the arrangement side and the opposite side of the lead frame 15 are stretched in the direction that the tip parts are isolated from the outer peripheral part of the aperture of a jig to be used when the through holes is filled with solder, and have slant stretching parts 142b.

66. 发明专利

JPH0878812A BONDING METHOD AND BONDING STRUCTURE FOR EXTERNAL CONNECTION LEAD AND WIRING BOARD 失效
公开(公告)号：JPH0878812A
公开(公告)日：1996-03-22
申请号：JP24050194
申请日：1994-09-07
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： C09J5/00 , H05K1/18 , H05K3/30 , H05K3/32 , H05K3/40
摘要： PURPOSE: To provide the bonding method and the bonding structure of an external connection lead and a wiring in which a final adhesive layer of desired thickness can be formed on the desired position of a limited region in a highly precise manner, and to lessen the thermal stress of an electric connection part after it is connected. CONSTITUTION: When the expected surface to be adhered to a wiring board 1, which is located on the side of board end part closer than the connection part which is electrically connected to the inner lead part 21 of an external connection lead 2, and the backside 22 of an inner lead part 21 are adhered, the A-stage bonding solution of a thermosetting bonding agent, having a liquid A;stage, a B-stage which is non-sticky after semihardened and C-stage after final hardening, is applied by printing. Then, a B-stage dry adhesive layer is formed by drying, and subsequently, a C-stage final adhesive layer 3 is formed by heat-curing. An adhesive operation can be conducted as far as to the side face of the inner lead part 21 and to the upper surface of the above-mentioned side face.

67. 发明专利

JP2014175406A Inductor part, manufacturing method of inductor part, and printed wiring board 审中-公开
标题翻译：电感器部件，电感器部件的制造方法和印刷电路板
公开(公告)号：JP2014175406A
公开(公告)日：2014-09-22
申请号：JP2013045545
申请日：2013-03-07
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： MANO YASUHIKO , YOSHIKAWA KAZUHIRO , YANO TOSHIMASA , KARIYA TAKASHI
IPC分类号： H01F17/00 , H01F17/04 , H01F41/04
摘要： PROBLEM TO BE SOLVED: To provide an inductor part having good inductance property (Q value).SOLUTION: An inductor part comprises inductor patterns 158A, 158C, 158E, and 158G; magnetic material layers 174A, 174C, and 174E provided between the inductor patterns 158A, 158C, 158E, and 158G; and a dielectric film 175G through which each magnetic material layer is formed on the corresponding inductor pattern. The inductor patterns are spaced apart from the magnetic material layers by 0.5-10 μm. In inverse proportion to the square of the distance, the strength of an electromagnetic field weakens and accordingly, eddy currents arising on surfaces of the inductor patterns become smaller. Therefore, Q value of the inductor part is never deteriorated.
摘要翻译：要解决的问题：提供具有良好的电感特性（Q值）的电感部分。解决方案：电感器部分包括电感图案158A，158C，158E和158G; 设置在电感器图案158A，158C，158E和158G之间的磁性材料层174A，174C和174E; 以及在对应的电感图案上形成有各磁性体层的电介质膜175G。电感图案与磁性材料层隔开0.5-10μm。与距离的平方成反比，电磁场的强度减弱，因此在电感图案的表面上产生的涡流变小。因此，电感器部分的Q值不会变差。

68. 发明专利

JP2014165218A Wiring board and method of manufacturing wiring board 审中-公开
标题翻译：接线板和制造接线板的方法
公开(公告)号：JP2014165218A
公开(公告)日：2014-09-08
申请号：JP2013032527
申请日：2013-02-21
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： LIU SHI GUO , KATO SHINOBU , KARIYA TAKASHI
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a wiring board the degree of freedom in design of which is enhanced, while making the occupied area compact.SOLUTION: A wiring board 10 includes a first base 20, and first insulating layers 51, 52 laminated on the first principal surface F and the second principal surface S of the first base 20. A via conductor structure 30 having a first through hole conductor 22 functioning as a signal wiring circuit transmitting a signal is embedded in the first base 20. In the first base 20, a second through hole conductor 40 functioning as a power supply or a ground wiring circuit, and penetrating the first base 20 is formed in an area other than the area where the via conductor structure 30 is embedded. The interval of wiring of the first through hole conductors 22 is smaller than the interval of wiring of the second through hole conductors 40.
摘要翻译：要解决的问题：为了提供一种布线板，其设计自由度得到提高，同时使占用面积紧凑。解决方案：布线板10包括第一基座20和层叠在第一绝缘层51,52上的第一绝缘层51,52。第一基底表面F和第一基底20的第二主表面S.具有用作传输信号的信号布线电路的第一通孔导体22的通孔导体结构30嵌入在第一基底20中。在第一基底20 在通孔导体结构30嵌入的区域以外的区域形成有用作电源或接地布线电路并贯通第一基座20的第二通孔导体40。第一通孔导体22的配线间隔小于第二通孔导体40的布线间隔。

69. 发明专利

JP2011211194A Wiring board and method for manufacturing the same 有权
标题翻译：接线板及其制造方法
公开(公告)号：JP2011211194A
公开(公告)日：2011-10-20
申请号：JP2011062080
申请日：2011-03-22
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI
IPC分类号： H05K1/14 , H01L23/12 , H01L25/04 , H01L25/18 , H05K3/00 , H05K3/46
CPC分类号： H05K1/0298 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L2224/16225 , H01L2224/1703 , H01L2924/15151 , H01L2924/15311 , H05K1/181 , H05K1/182 , H05K3/0047 , H05K3/4602 , H05K3/4623 , H05K3/4644 , H05K2201/10159 , H05K2201/10363 , H05K2201/10522 , H05K2201/1053 , H05K2201/10674 , Y02P70/611 , Y10T29/49155 , Y10T29/49165
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board that connects plural IC chips mounted thereon to each other at a short wire length.SOLUTION: In the printed wiring board, a signal pad 901b of a CPU 901 and a signal pad 902b of a memory 902, are arranged each on one side thereof, and mounted on a built-up multilayered wiring board 11, while the sides on which the signal pads are arranged are faced with each other. The signal pad 901b of the CPU and the signal pad 902b of the memory, are connected through a signal wire 83 of a heat-resistant board 80. The CPU and the memory are connected by a short signal wire 43 of the heat-resistant board 80, thereby achieving a high-capacity and high-speed transmission between the CPU and the memory.
摘要翻译：要解决的问题：提供一种印刷线路板，其以安装在其上的多个IC芯片以短线长度连接多个IC芯片。解决方案：在印刷线路板中，CPU 901的信号焊盘901b和存储器902各自布置在其一侧，并且安装在积层的多层布线板11上，而信号垫布置在其上的侧面彼此面对。 CPU的信号焊盘901b和存储器的信号焊盘902b通过耐热板80的信号线83连接。CPU和存储器通过耐热板的短信号线43连接 80，从而实现CPU和存储器之间的高容量和高速传输。

70. 发明专利

JP2010219503A Substrate for mounting semiconductor element and method of manufacturing the substrate for mounting the semiconductor element 有权
标题翻译：用于安装半导体元件的基板和制造用于安装半导体元件的基板的方法
公开(公告)号：JP2010219503A
公开(公告)日：2010-09-30
申请号：JP2010015153
申请日：2010-01-27
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , KOMATSU DAIKI
IPC分类号： H01L23/15 , H01L23/12
CPC分类号： H01L23/13 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5385 , H01L23/5387 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/12044 , H05K1/0306 , H05K1/144 , H05K1/183 , H05K3/4602 , H05K3/4605 , H05K3/4608 , H05K3/4691 , H05K3/4694 , H05K2201/0187 , H05K2201/055 , H05K2201/068 , H05K2201/09509 , H05K2201/10545 , H05K2201/10674 , H05K2203/063 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor element, in which fine-pitch wiring layers are formed to mount the semiconductor element and the reliability is not degraded by heat from the semiconductor element.
SOLUTION: In a semiconductor element mounting substrate 10, a low-thermal expansion substrate 50 is sandwiched between an interlayer resin layer 14U on the top surface and an interlayer resin layer 14D on the underside, and a conductor circuit 26 of an organic substrate 30 and a first conductor circuit 80 of the low-thermal expansion substrate 50 are connected via a via conductor 22 formed on the interlayer resin layer 14U. Thus the low-thermal expansion substrate 50 for mounting a semiconductor element 90 is connected to the organic substrate 30 that is connected to an external substrate, without arranging the organic substrate and the resin layers on the back side of the low-thermal expansion substrate 50 that is considerably affected by the thermal history of the semiconductor element 90.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种用于安装半导体元件的基板，其中形成微细间距布线层以安装半导体元件，并且可靠性不会受到来自半导体元件的热的影响。解决方案：在半导体元件安装基板10中，低热膨胀基板50夹在顶面的层间树脂层14U和下侧的层间树脂层14D之间，有机层的导体电路26 低热膨胀基板50的基板30和第一导体电路80经由形成在层间树脂层14U上的通路导体22连接。因此，用于安装半导体元件90的低热膨胀基板50连接到与外部基板连接的有机基板30，而不将有机基板和树脂层布置在低热膨胀基板50的背面这受到半导体元件90的热历史的很大影响。版权所有（C）2010，JPO＆INPIT

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