专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明专利

JPS6198461A Address conversion 失效
标题翻译：地址转换
公开(公告)号：JPS6198461A
公开(公告)日：1986-05-16
申请号：JP21830684
申请日：1984-10-19
申请人： Hitachi Ltd
发明人： FUKUDA MASAHARU , SAWAMOTO HIDEO
IPC分类号： G06F12/10
摘要： PURPOSE: To lighten the overhead of address conversion by installing a means for detecting that an address produced by a VM operating system wraps around and suppressing a carrier transfer from the highest order bit.
CONSTITUTION: The SX of a logical address register 11 and the STO of a segment table origin register 12 are inputted together with the α of a start address register 13 to an adder 41-1 and a logical operation circuit 42-1. When the output of a register 40 shows a 24-bit mode, the logical operation circuit 42-1 detects the presence or absence of a carrier from the highest order bit at an address due to addition only of STO and SX. When the address wraps around, the signal for suppressing the transfer of the carrier from the highest order bit is outputted to the adder 41-1.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过安装一个检测VM操作系统产生的地址的手段来折叠地址转换的开销，并抑制从最高位的载波传输来减轻地址转换的开销。构成：将逻辑地址寄存器11的SX和段表起始寄存器12的STO与起始地址寄存器13的α一起输入到加法器41-1和逻辑运算电路42-1。当寄存器40的输出显示24位模式时，逻辑运算电路42-1由于仅添加STO和SX而从地址的最高位开始检测载波的存在或不存在。当地址包围时，用于抑制载波从最高阶位传送的信号被输出到加法器41-1。

62. 发明专利

JPS60215265A ADDRESS CONVERSION SYSTEM 失效
公开(公告)号：JPS60215265A
公开(公告)日：1985-10-28
申请号：JP7080284
申请日：1984-04-11
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , ONODERA OSAMU
IPC分类号： G06F12/10
摘要： PURPOSE:To perform conversion into a real address of a real computer from a virtual address in the same processing time as that required for a bear machine, by using the same adder to perform simultaneously the addition of logical addresses of a virtual computer system and the addition of start addresses of a virtual resident computer system. CONSTITUTION:A logical address register 11 stores a virtual address, and this virtual address includes a segment index SX, a paging index PX and a byte index BX. The index SX, a segment table origin STO stored in a segment table origin register 12 and the contents alpha of a start address register 13 of a virtual resident computer are added simultaneously by a 3-input adder 31-1. Then qualification prefix conversion circuits 32-1-32-3 performs conversion successively to obtain a real address of a real computer corresponding to the virtual address stored in the register 11. This real address is stored to a real address register 22.

63. 发明专利

JPS6072030A INFORMATION PROCESSING DEVICE 失效
公开(公告)号：JPS6072030A
公开(公告)日：1985-04-24
申请号：JP17800583
申请日：1983-09-28
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SAWAMOTO HIDEO , TAKEDA KAZUMITSU , IKEDA KOUICHI
IPC分类号： G06F9/38 , G06F9/32
摘要： PURPOSE:To improve the performance of a branch instruction, etc. by detecting a fact that an instruction address exceeds a page boundary on the way of fetching in instruction if it occurs, and inhibiting storage of the subsequent data. CONSTITUTION:Data from a storage control device SUC is set to instruction buffer registers (hereinafter called IBR) 1-4 of 4-byte length each by the SUC and a WTIBR signal of 4 bytes. Also, an instruction buffer pointer (hereinafter called IBP) 5 indicates from which IBR an instruction to be executed in the next time is fetched. When a instruction address is in a 2-byte boundary and instruction length is above 2 bytes, the IBP5 indicates the head of the next instruction by 2-byte unit and is set to an instruction register IR6, the instruction length is added to the IBR by a 2-byte unit and updated so as to indicate the head of the next instruction. In this way, 16 bytes from an optional 4-byte boundary address can be fetched, and detched data can be stored in order from the IBR used most frequently in the past.

64. 发明专利

JPS6057449A ADDRESS CONVERSION SYSTEM FOR VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS6057449A
公开(公告)日：1985-04-03
申请号：JP16494883
申请日：1983-09-09
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , YAMADA TAKAFUMI
IPC分类号： G06F9/46 , G06F12/10
摘要： PURPOSE:To increase the multiplicity of a virtual computer without increasing the bits for identification of the virtual computer within an address conversion buffer, by providing a virtual computer identification number stack and a virtual computer identification number stack register. CONSTITUTION:The processing of a real computer is switched to an operating system VMOS of virtual computer identification number VMID=alpha, and the high- speed processing is carried out. If the bit number of a virtual address buffer TLB2 is set at (n), the maximum value l of the stack number of a VMID stack 8 is equal to 2 -1. Therefore the number alpha is registered to the stack to which the VMID of the oldest VMOS is registered when the stack 8 is already filled although the number alpha is not registered yet in case the VM multiplicity is larger than 2 -1. The corresponding stack number is set to a VMID stack register VMSNR9, and at the same time the corresponding entry of the TLB2 of the VMSN part is purged. Otherwise all entries of the stack 8 are invalidated and the number alpha is registered again to the stack 8.

65. 发明专利

JPS6051951A INPUT/OUTPUT PROCESSING DEVICE 失效
公开(公告)号：JPS6051951A
公开(公告)日：1985-03-23
申请号：JP15990283
申请日：1983-08-31
申请人： HITACHI LTD
发明人： UMENO HIDENORI , SAWAMOTO HIDEO
IPC分类号： G06F13/14 , G06F9/46 , G06F13/12
摘要： PURPOSE:To execute an input/output simulation processing at a high speed by executing the conversion of a virtual and an actual I/O addresses by hardware, when the interruption of a virtual computer is impossible by the hardware, in a virtual computer system. CONSTITUTION:When an I/O interrupting request is sent to an input/output processor 24 from each sub-channel 33, the interrupting request is read and that of high priority is selected. An I/O address is converted to a virtual address, and a virtual computer number (j) selected by a register 25, a virtual I/O address Vccuu and an actual I/O address (rccuu) are set. When the interrupting request is received, a CPU20 decides whether it is receivable or not. When the interruption is impossible as to the CPU20, an interruption impossible signal is sent to the input/output processor 24, interrupting information is stored in a store area 12, and thereafter, a request cue service is executed to process the next interruption.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式