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61. 发明专利

JP2008288813A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008288813A
公开(公告)日：2008-11-27
申请号：JP2007130980
申请日：2007-05-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KOBAYASHI TAKASHI , MACHIDA SHUNTARO
IPC分类号： H04R19/00 , B81B3/00 , H01L29/84
CPC分类号： B06B1/0292 , G01N29/2406
摘要： PROBLEM TO BE SOLVED: To improve the breakdown voltage of an intermetal insulating film and to suppress the charge trapping of the intermetal insulating film compatibly. SOLUTION: A lower electrode M0E is formed over a semiconductor substrate 1S via an insulator film 2, insulator films 5 and 7 are formed to cover the lower electrode M0E, an upper electrode M1E is formed over the insulator film 7, insulator films 9, 11 and 13 are formed to cover the upper electrode M1E, and a void VR is formed between the insulator films 5 and 7 between the lower electrode M0E and the upper electrode M1E. An ultrasonic transducer comprises the lower electrode M0E, the insulator film 5, the void VR, the insulator film 7 and the upper electrode M1E. At least a portion of the insulator film 5 contacting with the lower electrode M0E is made of silicon oxide, at least a portion of the insulator film 7 contacting with the upper electrode M1E is made of silicon oxide, and at least one of the insulator films 5 and 7 includes a silicon nitride film 5b positioned between the upper electrode M1E and the lower electrode M0E and not in contact with the upper electrode M1E or the lower electrode M0E. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提高金属间绝缘膜的击穿电压并且兼容地抑制金属间绝缘膜的电荷捕获。解决方案：通过绝缘膜2在半导体衬底1S上形成下电极M0E，形成绝缘膜5和7以覆盖下电极M0E，在绝缘膜7上形成上电极M1E，绝缘膜 9,11和13形成为覆盖上电极M1E，并且在下电极M0E和上电极M1E之间的绝缘膜5和7之间形成空隙VR。超声波换能器包括下电极M0E，绝缘膜5，空隙VR，绝缘膜7和上电极M1E。与下部电极M0E接触的绝缘膜5的至少一部分由氧化硅构成，与上部电极M1E接触的绝缘膜7的至少一部分由氧化硅构成，绝缘膜的至少一方 5和7包括位于上电极M1E和下电极M0E之间并且不与上电极M1E或下电极M0E接触的氮化硅膜5b。版权所有（C）2009，JPO＆INPIT

62. 发明专利

JP2008211891A Digital protection relay 审中-公开
标题翻译：数字保护继电器
公开(公告)号：JP2008211891A
公开(公告)日：2008-09-11
申请号：JP2007045305
申请日：2007-02-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIDO MITSUYASU , KOBAYASHI TAKASHI , SATO MITSUO
IPC分类号： H02H3/05
摘要： PROBLEM TO BE SOLVED: To simplify the configuration while ensuring reliability of a digital protection relay. SOLUTION: The digital protection relay comprises a plurality of multiplexed analog filters 2a and 2b for filtering the analog AC electrical quantity, and a plurality of multiplexed microcontrollers 3a and 3b of identical configuration. The plurality of microcontrollers 3a and 3b operate with an identical clock outputted from a common clock signal source 19, and output a protection command by ANDing the protection operation results outputted from the plurality of multiplexed microcontrollers 3a and 3b at an identical timing. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了简化配置，同时确保数字保护继电器的可靠性。解决方案：数字保护继电器包括用于对模拟AC电量进行滤波的多路复用模拟滤波器2a和2b以及具有相同结构的多路复用微控制器3a和3b。多个微控制器3a和3b以从公共时钟信号源19输出的相同时钟进行工作，并通过在相同的定时对与多个多路复用的微控制器3a和3b输出的保护操作结果进行AND运算来输出保护命令。版权所有（C）2008，JPO＆INPIT

63. 发明专利

JP2007312525A Digital protection control apparatus 有权
标题翻译：数字保护控制装置
公开(公告)号：JP2007312525A
公开(公告)日：2007-11-29
申请号：JP2006139680
申请日：2006-05-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIDO MITSUYASU , KOMATSU SHINJI , KOBAYASHI TAKASHI , SATO MITSUO
IPC分类号： H02H3/05
摘要： PROBLEM TO BE SOLVED: To solve the problem, wherein a scale of hardware becomes large since hardware of main detection and that of accident detection are completely separated so that unnecessary operations are not performed due to the fault of a single component in conventional cases, that the volume of a continuous monitor processing becomes large except for a protection control operation that serves as application, since hardware defects are detected in the continuous monitor processing, and that recognition tests for recognizing the functions of continuous monitor increase. SOLUTION: A harmonic superposed signal is applied to an analog signal processing circuit at all times, the output of the analog input signal processing circuit is A/D-converted, data are inputted to CPU having a double configuration, and the harmonic superposed signal is extracted at each calculation period. Accordingly, the result is collated with a protection operation/sequence processing result for performing tripping. By having a time difference given to starting signals calculating CPU, having the double configuration, and the same processing executed, both results are collated at each sampling, soundness of a collation circuit is confirmed also. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决问题：为了解决硬件规模变大的问题，因为主检测和事故检测的硬件完全分离，使得由于常规的单个部件的故障而不执行不必要的操作情况下，连续监视处理的量变大，除了用作应用程序的保护控制操作，因为在连续监视处理中检测到硬件缺陷，并且用于识别连续监视器的功能的识别测试增加。解决方案：模拟信号处理电路一直对谐波叠加信号进行A / D转换，数据输入到具有双重配置的CPU，并且谐波在每个计算周期提取叠加信号。因此，结果与用于执行跳闸的保护操作/顺序处理结果进行整理。通过对计算CPU的启动信号给出具有双重配置的时间差，并且执行相同的处理，在每次采样时对这两个结果进行整理，也确认了对照电路的良好性。版权所有（C）2008，JPO＆INPIT

64. 发明专利

JP2007020329A Digital protection and control device 有权
标题翻译：数字保护和控制装置
公开(公告)号：JP2007020329A
公开(公告)日：2007-01-25
申请号：JP2005200202
申请日：2005-07-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIDO MITSUYASU , CHIBA TOMIO , SATO MITSUO , KOBAYASHI TAKASHI , NAGAYAMA KAZUYUKI
IPC分类号： H02H3/02
摘要： PROBLEM TO BE SOLVED: To provide a digital protection and control device that facilitates the expansion or the consolidation of functions. SOLUTION: The digital protection and control device includes protection computing means 1a that carries out main detection processing, based on a system signal 1l fetched via an input converter 1k; digital input/output means 1b on the main detection side; protection computing means 1d that carries out outage detection computation processing; and digital input/output means 1e on the outage detection side. Furthermore, the means 1a, 1c and 1d are provided with a common memory 100. Each element is provided with a communication controller, and all the elements are connected together, through a serial bus 3a constituted of fixed-frequency protocol communication means. Since the serial bus 3 is provided with a bus master function, with which all the elements can acquire the bus right and the elements carry out data transmission among them at a fixed frequency, real-time protection and control can be achieved. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供便于扩展或功能合并的数字保护和控制设备。数字保护和控制装置包括基于通过输入转换器1k提取的系统信号111执行主检测处理的保护计算装置1a; 主检测侧的数字输入/输出装置1b; 执行中断检测计算处理的保护计算装置1d; 和中断检测侧的数字输入/输出装置1e。此外，装置1a，1c和1d设置有公共存储器100.每个元件设置有通信控制器，并且所有元件通过由固定频率协议通信装置构成的串行总线3a连接在一起。由于串行总线3具有总线主控功能，所有的元件都可以通过该功能获取总线权限，并且元件以固定的频率在它们之间进行数据传输，因此可以实现实时保护和控制。版权所有（C）2007，JPO＆INPIT

65. 发明专利

JP2005218220A Digital protection controller 审中-公开
标题翻译：数字保护控制器
公开(公告)号：JP2005218220A
公开(公告)日：2005-08-11
申请号：JP2004021700
申请日：2004-01-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KOBAYASHI TAKASHI , KIDO MITSUYASU
IPC分类号： H02H3/02 , H02H3/00 , H02J13/00
摘要： PROBLEM TO BE SOLVED: To confirm the validity of data and correct failed data even if a serial transfer system is introduced into a system bus. SOLUTION: Units 3, 4, 8 and 10 are connected via a serial link 7, and when data are outputted from a transmitting circuit 33 to the serial link 7, an error correction code is added to the transmitted data and outputted as the serial data. A receiving circuit 34 for receiving the serial data from the serial link 7 determines the validity of the data based on the error correction code in the received data, corrects the received data when an abnormality is detected, and receives the corrected data. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使将串行传输系统引入系统总线，也可以确认数据的有效性和纠正失败的数据。解决方案：单元3,4,8和10通过串行链路7连接，当数据从发送电路33输出到串行链路7时，将错误校正码加到发送数据上并作为串行数据。用于从串行链路7接收串行数据的接收电路34基于接收到的数据中的纠错码确定数据的有效性，当检测到异常时对接收的数据进行校正，并接收校正的数据。版权所有（C）2005，JPO＆NCIPI

66. 发明专利

JP2005101174A Non-volatile semiconductor storage device and method for manufacturing the same 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2005101174A
公开(公告)日：2005-04-14
申请号：JP2003331546
申请日：2003-09-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKO YOSHITAKA , KOBAYASHI TAKASHI
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0433 , G11C16/0491 , H01L27/115 , H01L29/42328 , H01L29/42336
摘要： PROBLEM TO BE SOLVED: To promote the realization of higher integration density and higher performance of a non-volatile semiconductor storage device which utilizes an inverting layer formed on a semiconductor substrate as a data line.
SOLUTION: A memory cell is formed of a MOS transistor comprising a floating gate 6, a control gate 7 forming the word line WL, and an embedded gate 8. The embedded gate 8 is embedded within a groove 2 formed on the self-alignment basis for the floating gate 6. The embedded gate 8 and the upper control gate 7 are insulated via a thick silicon oxide film 10 at the upper part of the groove 2 and a second gate insulating film 5 at the upper part of the film 10. The source and drain of the memory cell are constituted by an inverting layer (local data line) formed in a p-type well 3 at the lower part of the embedded gate 8 when a positive voltage is applied to the embedded gate 8.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：为了促进利用形成在半导体衬底上的反相层作为数据线的非易失性半导体存储器件的更高的集成密度和更高性能的实现。解决方案：存储单元由包括浮置栅极6，形成字线WL的控制栅极7和嵌入栅极8的MOS晶体管形成。嵌入式栅极8嵌入形成在自身上的沟槽2内浮置栅极6的对准基础。嵌入栅极8和上部控制栅极7通过在沟槽2的上部的厚氧化硅膜10和在膜的上部的第二栅极绝缘膜5绝缘当向嵌入式门8施加正电压时，存储单元的源极和漏极由形成在嵌入式栅极8的下部的p型阱3中的反相层（局部数据线）构成。版权所有（C）2005，JPO＆NCIPI

67. 发明专利

JP2004248477A Digital protective relay 有权
公开(公告)号：JP2004248477A
公开(公告)日：2004-09-02
申请号：JP2003038729
申请日：2003-02-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIDO MITSUYASU , SATO MITSUO , KOBAYASHI TAKASHI
IPC分类号： H02H3/02 , H03H17/00 , H03H17/02
CPC分类号： H02H1/0092
摘要： PROBLEM TO BE SOLVED: To miniaturize a circuit element of an analog circuit by high-speed sampling. SOLUTION: Analog signals obtained through analog filters 12a-12n are inputted via a multiplexer 14. These analog signals are converted into digital data by an A-D converter 20. When processed by a digital filter 22, the digital data are sampled at a frequency which is eight times as high that of a sampling frequency to generate high-frequency digital data made by this over sampling. Then, these data are thinned out and stored in a buffer memory 24 as 2,400 Hz data. These data are inputted into a CPU 28 to execute protective operations and to output a protective signal for a power system to a device to be protected via an input/output portion 36. COPYRIGHT: (C)2004,JPO&NCIPI

68. 发明专利

JP2003318287A Nonvolatile semiconductor memory and its fabricating method 审中-公开
标题翻译：非线性半导体存储器及其制造方法
公开(公告)号：JP2003318287A
公开(公告)日：2003-11-07
申请号：JP2002117471
申请日：2002-04-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKO YOSHITAKA , KOBAYASHI TAKASHI
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To avoid decrease of the coupling ratio resulting from the difficulty of collective machining of a control gate material, an interlayer insulation film material and a floating gate material incident to reduction in the width of a word line of a nonvolatile semiconductor memory, and to avoid damage on a gate oxide film at the time of collective machining. SOLUTION: Prior to fabricating the floating gate of a memory cell in a nonvolatile memory, a space surrounded on all sides by an insulation film is made for the floating gate of each cell such that each floating gate is buried in each space. It can be realized through self-aligned machining of the floating gate following to deposition of a floating gate material film. Since collective machining of a control gate material, an interlayer insulation film material and a floating gate material is not required at the time of machining a control gate, a sufficient interlayer insulation film capacity can be ensured. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了避免由于控制栅极材料的集中加工的困难而导致的耦合率的降低，层间绝缘膜材料和浮动栅极材料的入射，以减少字线的字线的宽度非易失性半导体存储器，并且避免在集体加工时对栅极氧化膜的损坏。解决方案：在制造非易失性存储器中的存储单元的浮置栅极之前，为每个单元的浮置栅极制造由绝缘膜所包围的空间，使得每个浮置栅极被埋在每个空间中。可以通过在浮栅材料膜的沉积之后对浮栅进行自对准加工来实现。由于在加工控制栅极时不需要控制栅极材料的集成加工，层间绝缘膜材料和浮栅材料，因此可以确保足够的层间绝缘膜容量。版权所有（C）2004，JPO

69. 发明专利

JP2003168748A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2003168748A
公开(公告)日：2003-06-13
申请号：JP2001366870
申请日：2001-11-30
申请人： HITACHI LTD
发明人： KOBAYASHI TAKASHI
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make a non-volatile semiconductor memory device minute or highly reliable. SOLUTION: The non-volatile semiconductor memory device is constituted of a source/drain diffusion layer 105 in a p-type well 101 formed on a silicone substrate 100, a first gate or a floating gate 107b, a second gate or a control gate (word line) 110a and a third gate 103a. The thickness of a tunnel insulation film 106a is made larger compared with that of a gate insulation film 102 in a memory cell, in which the floating gate 107b is separated from the p-type well 101 by the tunnel insulation film 106a, the third gate 103a is separated from the p-type well 101 by the gate insulation film 102, the floating gate 107b is separated from the third gate 103a by the insulation film 106b, the floating gate 107b is separated from the word line (control gate) 110a by an insulation film (ONO film) 109a and the third gate 103a is separated from the word line (control gate) 110a by a silicone oxide film 104b respectively. COPYRIGHT: (C)2003,JPO

70. 发明专利

JP2002368144A Non-volatile semiconductor memory device and production method therefor 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2002368144A
公开(公告)日：2002-12-20
申请号：JP2001177928
申请日：2001-06-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKO YOSHITAKA , KOBAYASHI TAKASHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To improve punch-through resistance between a source and a drain with the reduction of a cell area in a non-volatile semiconductor memory device, without causing deterioration in bonding pressure resistance between a diffusing layer and a well. SOLUTION: The impurity of the same conductive type, as a well 201, is doped in a channel region between source/drain diffusing layers 205 so as not to contact the diffusing layers 205. While using mutually reverse oblique ion injections with a previously formed gate 207a as a mask, a heavily-doped region 501 of the same conductive type as that of the diffusion layers 205 and the well is formed in self-aligned manner to the gate 207a.
摘要翻译：要解决的问题：通过减少非易失性半导体存储器件中的单元面积来提高源极和漏极之间的穿透电阻，而不会导致扩散层和阱之间的结合压力电阻的劣化。解决方案：作为阱201的相同导电类型的杂质掺杂在源/漏扩散层205之间的沟道区域中，以便不与扩散层205接触。当使用相互反向的倾斜离子注入与先前形成的栅极 207a作为掩模，与扩散层205和阱的导电类型相同的重掺杂区域501以与栅极207a自对准的方式形成。

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