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51. 发明专利

JP2009188699A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2009188699A
公开(公告)日：2009-08-20
申请号：JP2008025994
申请日：2008-02-06
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAKIDO KAZUO , NAKAMURA HOMARE
IPC分类号： H03L7/06 , H03K3/03 , H03K3/354 , H03K5/135 , H03K19/096 , H03L7/081
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/093 , H03L2207/50
摘要： PROBLEM TO BE SOLVED: To reduce steps of storing control information to a register, which digitally controls a clock signal generating part. SOLUTION: This semiconductor integrated circuit includes a digital control signal generating part 10 to generate a clock signal CLKm, and a clock generating part equipped with a digital control part 20. The clock generating part is further equipped with a phase frequency comparator 31, and a control register 22. A reference signal CLKin and a feedback signal Mout are supplied to the comparator 31. The output signal FDout of the comparator 31 is supplied to the control resistor 22, and the control resistor 22 stores digital control information composed of a plurality of bits. The clock generating part is further equipped with a control data storage circuit 25 to store a plurality of initial setting data for a plurality of locking operations in advance. The initial setting data Sset1-Sset5 are stored in the high-order bits of the control resister 22 from the control data storage circuit 25 in response to operation selection information Min. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少将控制信息存储到数字控制时钟信号产生部分的寄存器的步骤。解决方案：该半导体集成电路包括用于产生时钟信号CLKm的数字控制信号产生部分10和配备有数字控制部分20的时钟产生部分。时钟产生部分还配备有相位频率比较器31 和控制寄存器22.参考信号CLKin和反馈信号Mout被提供给比较器31.比较器31的输出信号FDout被提供给控制电阻器22，并且控制电阻器22存储由多个位。时钟产生部分还配备有控制数据存储电路25，用于预先存储用于多个锁定操作的多个初始设置数据。响应于操作选择信息Min，初始设置数据Sset1-Sset5从控制数据存储电路25存储在控制寄存器22的高位中。版权所有（C）2009，JPO＆INPIT

52. 发明专利

JP4300471B2 Arbitrary waveform synthesizer to use a free-running ring oscillator 有权
公开(公告)号：JP4300471B2
公开(公告)日：2009-07-22
申请号：JP2003581342
申请日：2002-03-25
申请人：アルテラコーポレイションAltera Corporation
发明人：カーリー，アダム，エル．
IPC分类号： H03K3/64 , H03K5/14 , B41J2/045 , B41J2/205 , B41J29/38 , G06F1/02 , G06F15/00 , G06K1/00 , H03B20060101 , H03B21/00 , H03K3/03 , H03K3/84 , H03K5/13 , H03K5/135 , H03K5/159 , H04N1/40 , H04N1/46
CPC分类号： G06F1/022 , G06F1/025 , H03K5/133 , H03K5/159 , H03L7/0814 , H03L7/16

53. 发明专利

JP2009512050A Smart card that includes a method and circuit for local clock generation, as well as the same clock on 有权
公开(公告)号：JP2009512050A
公开(公告)日：2009-03-19
申请号：JP2008535126
申请日：2006-10-06
申请人：アクサルト・エス・アー , エスティマイクロエレクトロニクスエスエー
发明人：デユバル，バンジヤマン , ポメー，アラン , レデイエ，ロベール
IPC分类号： G06F1/04 , G06F1/06 , G06K19/07 , H03K5/00 , H03K5/135
CPC分类号： G06F1/04 , H03K5/133 , H03K5/135 , H03K5/156 , H03K2005/00058 , H04L7/0338
摘要：１つの遅延回路がクロック回復の正確度を改善するためのクロック回復回路内部の開ループ内に挿入される。１つの発振器信号φ（０）〜φ（２
ｉ −１）が基本タイムステップと共に提供される。あるビット持続時間に相当するタイムステップの有理数が、受け取られたビットフロー内で測定される。発振器信号φ（０）〜ｊ（２
ｉ −１）が少なくとも１つの発振器信号φ（０）〜φ（２
ｉ −１）と同調する前記クロック信号のアクティブエッジを有するクロック信号ＣＫに変換され、連続する２つのアクティブエッジが、タイムステップの数の整数部分に比例する持続時間によって分離される。タイムステップの数の小数部分に比例する時間遅延が計算される。クロック信号ＣＫの次のアクティブエッジが前記計算された遅延で遅延される。

54. 发明专利

JP2009017151A Delay circuit and signal generating circuit using the same 审中-公开
标题翻译：延迟电路和信号发生电路
公开(公告)号：JP2009017151A
公开(公告)日：2009-01-22
申请号：JP2007175709
申请日：2007-07-04
申请人： Yokogawa Electric Corp , 横河電機株式会社
发明人： KUWABARA HIROSUKE
IPC分类号： H03K5/135 , G01R31/3183 , H03L7/00 , H03L7/081
摘要： PROBLEM TO BE SOLVED: To solve the problem that an offset delay time of a programmable delay circuit changes according to circumference conditions such as ambient temperature, so that an output waveform signal of a signal generating circuit using this programmable delay circuit is unstable. SOLUTION: The programmable delay circuit is series-connected to a delay circuit to input clocks into the programmable delay circuit, a delay time of the programmable delay circuit is controlled so as to provide a constant total delay time of the two delay circuits, and also an output of the programmable delay circuit is inputted into a plurality of programmable delay circuits. Further, the signal generating circuit is configured by use of the plurality of programmable delay circuits. Even if the circumference conditions change, the delay time with respect to clocks of the plurality of programmable delay circuits does not change. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了解决可编程延迟电路的偏移延迟时间根据诸如环境温度的周围条件而变化的问题，使得使用该可编程延迟电路的信号发生电路的输出波形信号不稳定。解决方案：可编程延迟电路串联连接到延迟电路以将时钟输入到可编程延迟电路中，可编程延迟电路的延迟时间被控制，以便提供两个延迟电路的恒定总延迟时间，并且可编程延迟电路的输出也被输入到多个可编程延迟电路中。此外，信号发生电路通过使用多个可编程延迟电路来配置。即使圆周条件改变，相对于多个可编程延迟电路的时钟的延迟时间也不改变。版权所有（C）2009，JPO＆INPIT

55. 发明专利

JP2008306699A Frequency adjusting apparatus and dll circuit including same 审中-公开
标题翻译：频率调整装置和DLL电路，包括它们
公开(公告)号：JP2008306699A
公开(公告)日：2008-12-18
申请号：JP2008040598
申请日：2008-02-21
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： CHO KOSHUN , CHUN JUN HYUN
IPC分类号： H03L7/081 , G06F1/10 , H03K5/135 , H03K5/156 , H04L7/02
CPC分类号： H03L7/0814
摘要： PROBLEM TO BE SOLVED: To provide a frequency adjusting apparatus for reducing electromagnetic interference of a semiconductor integrated circuit, and a delay locked loop (DLL) circuit including the same. SOLUTION: A frequency adjusting apparatus of the present invention is characterized in including a frequency control signal generating section for generating a frequency control signal, with a plurality of bits, which is level-shifted bit by bit in response to a reference clock, and a frequency adjusting section which adjusts a frequency of the inputted reference clock in response to the frequency control signal with the plurality of bits. Furthermore, a frequency adjusting apparatus of another invention is characterized in including a frequency control signal generating section for generating a frequency control signal with a plurality of bits by dividing the frequency of a reference clock in a plurality of frequency dividing ratios, and a frequency adjusting section for adjusting a frequency of the inputted reference clock in response to the frequency control signal with the plurality of bits. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于减小半导体集成电路的电磁干扰的频率调节装置，以及包括该频率调节装置的延迟锁定环（DLL）电路。解决方案：本发明的频率调整装置的特征在于包括频率控制信号产生部分，用于产生频率控制信号，多个比特是响应于参考时钟逐位移位以及频率调整部，其响应于具有多个位的频率控制信号来调整输入的基准时钟的频率。此外，另一发明的频率调整装置的特征在于包括：频率控制信号生成部，其通过以多个分频比除以参考时钟的频率，生成具有多个位的频率控制信号;频率调整部分，用于响应于具有多个位的频率控制信号来调节输入的参考时钟的频率。版权所有（C）2009，JPO＆INPIT

56. 发明专利

JP2008271554A Semiconductor switch with integrated delay circuit 审中-公开
标题翻译：具有集成延迟电路的半导体开关
公开(公告)号：JP2008271554A
公开(公告)日：2008-11-06
申请号：JP2008107867
申请日：2008-04-17
申请人： Catem Develec Gmbh & Co Kg , カテム・デヴェレック・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング・ウント・コンパニー・コマンデイト・ゲゼルシャフト
发明人： UHL GUENTER , WANDRES STEFFEN
IPC分类号： H03K17/687 , H03K5/135
CPC分类号： H03K17/687 , F02P19/023 , H03K17/08 , H03K17/162 , H03K17/284
摘要： PROBLEM TO BE SOLVED: To provide an integrated semiconductor switch on the basis of which a circuit for generating phase-shifted PWM signals can be realized at a reasonable price.
SOLUTION: An output stage for PWM control of a load stage with a delay circuit which, in addition to the load current modulated by a PWM input signal, supplies a PWM output signal that is delayed by a predetermined fraction of the period duration relative to the PWM input signal. The output stage can especially be realized by integrating the delay circuit together with the actual power semiconductor switch and an associated monitoring and control circuit in a single component. By cascading such output stages, a controller for phase-shifted PWM control of multi-stage loads, which is independent of a precise time base, can be realized in a simple manner.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供集成半导体开关，在此基础上，可以以合理的价格实现用于产生相移PWM信号的电路。解决方案：用于具有延迟电路的负载级的PWM控制的输出级，该延迟电路除了由PWM输入信号调制的负载电流之外还提供延迟了周期持续时间的预定分数的PWM输出信号相对于PWM输入信号。输出级可以通过将延迟电路与实际的功率半导体开关和相关的监视和控制电路集成在一个单独的部件中来实现。通过级联这种输出级，可以以简单的方式实现用于独立于精确时基的多级负载的相移PWM控制的控制器。版权所有（C）2009，JPO＆INPIT

57. 发明专利

JP4162810B2 Timing phase calibration method and a device for a semiconductor device testing apparatus 有权
公开(公告)号：JP4162810B2
公开(公告)日：2008-10-08
申请号：JP28816499
申请日：1999-10-08
申请人：株式会社アドバンテスト
发明人：幹雄菅
IPC分类号： G01R31/28 , G01R35/00 , H03K5/135

58. 发明专利

JP2008177638A Delay circuit 审中-公开
标题翻译：延时电路
公开(公告)号：JP2008177638A
公开(公告)日：2008-07-31
申请号：JP2007006643
申请日：2007-01-16
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： KOIKE TOMOYUKI , SAKURAI ATSUSHI , SANO KAZUSUKE
IPC分类号： H03K5/135 , H02J7/00
摘要： PROBLEM TO BE SOLVED: To reduce the circuit scale of a delay circuit which delays and outputs an input signal.
SOLUTION: The delay circuit has an OSC 11, a counter 12 which is connected to the OSC 11 and divides the frequency of a signal from the OSC 11, and a counter 13 which is connected to the OSC 11 through a switch 14 to frequency-divide the signal from the OSC 11 or connected to the counter 12 through a switch 15 to frequency-divide a signal from the counter 12.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少延迟和输出输入信号的延迟电路的电路规模。解决方案：延迟电路具有OSC 11，连接到OSC 11的计数器12，并且分频来自OSC11的信号的频率以及通过开关14连接到OSC 11的计数器13 通过开关15对来自OSC 11的信号进行分频或连接到计数器12，以对来自计数器12的信号进行分频。（C）2008，JPO＆INPIT

59. 发明专利

JP4002811B2 Multi-strobe generation equipment, test equipment, and adjustment method 有权
公开(公告)号：JP4002811B2
公开(公告)日：2007-11-07
申请号：JP2002292770
申请日：2002-10-04
申请人：株式会社アドバンテスト
发明人：新哉佐藤 , 優土井 , 崇長谷川
IPC分类号： G01R31/28 , G11C29/56 , G01R31/3183 , G01R31/319 , G11C11/401 , G11C29/00 , H03K5/135 , H03K5/1532 , H04L7/00 , H04L7/033
CPC分类号： G11C29/56 , G01R31/31922 , G11C29/028 , G11C29/56012 , H03K5/135 , H04L7/0337

60. 发明专利

JP2007288749A Delay circuit 审中-公开
标题翻译：延时电路
公开(公告)号：JP2007288749A
公开(公告)日：2007-11-01
申请号：JP2006118386
申请日：2006-04-21
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OTSUKA KENJI , WADA ATSUSHI
IPC分类号： H03K5/135
摘要： PROBLEM TO BE SOLVED: To solve problems of a conventional delay circuit that a configuration for controlling the number of delay stages is complicated and further there is danger to lack accuracy in precise delay control. SOLUTION: In a delay circuit 10, a first delay unit 12 includes a plurality of delay elements as an object to detect delay characteristics. A second delay unit 14 includes a plurality of delay elements for outputting signals delayed in accordance with the delay characteristics of the first delay unit 12. A detection unit 16 detects the number of delay elements used in the first delay unit 12 to delay an input signal just by a predetermined reference time. A selection unit 18 selects the number of delay elements used in the second delay unit 14 to delay the input signal in accordance with the detected number of delay elements. In the first delay unit 12 and the second delay unit 14, the ratio between each of the delay values of the delay elements included therein is equivalent to the ratio between the reference time and a desired delay time in the second delay unit 14. The delay values of the delay elements included in the second delay unit 14 are smaller than the delay values of the delay elements included in the first delay unit 12. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了解决用于控制延迟级数的结构复杂的传统延迟电路的问题，进一步存在精确的延迟控制的精度不足的危险。解决方案：在延迟电路10中，第一延迟单元12包括多个延迟元件作为检测延迟特性的对象。第二延迟单元14包括用于输出根据第一延迟单元12的延迟特性延迟的信号的多个延迟元件。检测单元16检测在第一延迟单元12中使用的延迟元件的数量，以延迟输入信号只是预定的参考时间。选择单元18选择在第二延迟单元14中使用的延迟元件的数量，以根据检测到的延迟元件的数量来延迟输入信号。在第一延迟单元12和第二延迟单元14中，其中包括的延迟元件的每个延迟值之间的比率等于第二延迟单元14中基准时间与期望延迟时间之间的比率。延迟包括在第二延迟单元14中的延迟元件的值小于包括在第一延迟单元12中的延迟元件的延迟值。（C）2008，JPO和INPIT

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