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51. 发明专利

JPH05268114A 失效
公开(公告)号：JPH05268114A
公开(公告)日：1993-10-15
申请号：JP6581692
申请日：1992-03-24
IPC分类号： H04B1/62 , H04B14/04 , H04J3/18
摘要： PURPOSE:To attain band compression while suppressing a high frequency band, that is, distortion at a high sound frequency by allowing a band compression section to receive a digital audio signal being an output of a de-emphasis section, to implement band compression by means of differential coding and to output the result. CONSTITUTION:The compressor is provided with a de-emphasis section 1 which receives a digital audio signal subject to emphasis in compliance with a determined standard and converts the input signal into a signal with a flat frequency characteristic with a so-called reverse operation as passing through a prescribed filter and with a band compression section 2 receiving the digital audio signal and implementing band compression through differential coding. Then the external digital audio signal subjected to emphasis from an upperstream is inputted to the de-emphasis section, in which the emphasis is released and then the result is inputted to the band compression section 2, in which the signal is subjected to band compression processing through differential coding and the result is outputted to the outside of a downstream. Thus, the signal is outputted to the outside of the downstream after band compression is implemented while suppressing distortion at a high frequency band.

52. 发明专利

JPH0566777B2 失效
公开(公告)号：JPH0566777B2
公开(公告)日：1993-09-22
申请号：JP1475785
申请日：1985-01-29
申请人： NIPPON ELECTRIC CO
发明人： MORIMURA HIROSHI
IPC分类号： H04J1/00 , H04J1/14 , H04J3/18

53. 发明专利

JPH04507038A 失效
公开(公告)号：JPH04507038A
公开(公告)日：1992-12-03
申请号：JP51153190
申请日：1990-07-24
IPC分类号： H04J3/04 , H04J3/18 , H04J99/00 , H04M11/06 , H04Q3/60 , H04Q11/04

54. 发明专利

JPS61167239A DATA SPEED CONVERTING CIRCUIT 失效
公开(公告)号：JPS61167239A
公开(公告)日：1986-07-28
申请号：JP869585
申请日：1985-01-21
申请人： NEC CORP
发明人： USAMI MASAHIKO
IPC分类号： H04J3/06 , H04J3/18
摘要： PURPOSE:To obtain an output signal converted into an 8-bit speed from a position of a synchronizing signal independently of a frequency of a high-speed clock by forming a 2-1 selection circuit controlled by a load signal and a latch circuit connected in cascade with the selection circuit to form a parallel/serial converting circuit. CONSTITUTION:A signal from the inside of a load signal generating circuit 14-2 of a control signal generating circuit 14 stops a counter at a prescribed value, the content is decoded to generate a load signal. Since a 2-1 selection circuit 15-2 or the like controlled by the said load signal and a latch circuit 15-1 or the like connected in cascade with the said 2-1 selection circuit form a parallel/serial converting circuit 15, an output signal subjected to speed conversion in an 8-bit from the location of the synchronizing signal is obtained independently of the high-speed clock frequency.

55. 发明专利

JPS60214133A Data converting circuit 失效
标题翻译：数据转换电路
公开(公告)号：JPS60214133A
公开(公告)日：1985-10-26
申请号：JP7040884
申请日：1984-04-09
申请人： Fujitsu Ltd
发明人： IYOTA TOSHIO , OGURA TAKAYUKI , HASHIMOTO KENICHI , SHIRAI HIROAKI
IPC分类号： H04J3/00 , H04J3/18
CPC分类号： H04J3/18
摘要： PURPOSE:To decrease the converting delay time by storing data of a specific channel of a multiplex serial form to the 1st memory, reading the data in a burst way and applying prescribed converting processing, storing it in the 2nd memory and reading it. CONSTITUTION:A counter CRT1 designates a write address to a memory MEM1, gives a write command to a selector SEL1, writes a specific channel CH on the MEM1 sequentially, confirms the final m-th specific CH data inputted to the MEM1, reads the 1st m-th specific CH data in a burst way and applies a prescribed converting processing by a read processing circuit PRO. A counter CTR2 designates an address to a memory MEM2, writes the specific CH data on the MEM2 finished for processing via a selector SEL2, starts reading at the transmission point of time of the 1st specific CH of the next frame and transmits the processed data via the selector SEL. Thus, the delay time required for two frames in conventional systems is decreased to that of one frame's share.
摘要翻译：目的：通过将多路复用串行格式的特定通道的数据存储到第一个存储器来减少转换延迟时间，以突发方式读取数据并应用规定的转换处理，将其存储在第二个存储器中并读取。构成：计数器CRT1向存储器MEM1指定写入地址，向选择器SEL1发出写入命令，依次向MEM1写入特定的通道CH，确认输入到MEM1的最后的第m个特定CH数据，读取第1个 m特定CH数据，并通过读处理电路PRO执行规定的转换处理。计数器CTR2表示存储器MEM2的地址，经由选择器SEL2将特定CH数据写入已经完成处理的MEM2，在下一帧的第1特定CH的发送时刻开始读取，并经由选择器SEL。因此，传统系统中两帧所需的延迟时间减少到一帧的份额。

56. 发明专利

JPS5934024B2 JPS5934024B2 - 失效
公开(公告)号：JPS5934024B2
公开(公告)日：1984-08-20
申请号：JP14822475
申请日：1975-12-11
申请人： Matsushita Electric Ind Co Ltd
发明人： NAKABE KOJI
IPC分类号： H04B1/66 , H04J3/00 , H04J3/18
CPC分类号： H04J3/18

57. 发明专利

JP2005130090A Video transmitter, receiver, video transmission system, video transmission method, video transmitting program, and recording medium with the video sending program stored 审中-公开
标题翻译：视频发射器，接收器，视频传输系统，视频传输方法，视频传输程序和记录媒体与视频发送程序存储
公开(公告)号：JP2005130090A
公开(公告)日：2005-05-19
申请号：JP2003361771
申请日：2003-10-22
申请人： Sharp Corp , シャープ株式会社
发明人： HOUGIYOKU TSUKURU
IPC分类号： H04N5/765 , H04J3/18 , H04N5/38 , H04N5/76 , H04N7/173 , H04N21/436 , H04N21/4402 , H04N21/442
CPC分类号： H04N21/4334 , H04N21/4108 , H04N21/4135 , H04N21/4143 , H04N21/4147 , H04N21/42204 , H04N21/42661 , H04N21/432 , H04N21/4363 , H04N21/43637
摘要： PROBLEM TO BE SOLVED: To provide a system, by which video data is sent to a receiver from a PC (a video transmitter) 1 and is reproduced, without being provided with an external input means providing an operation instruction to the PC 1 in the system composed of the PC 1 storing the video data and a receiver 2 receiving the video data, and to provide a system by which the PC 1 can send the video data, according with the function of the receiver. SOLUTION: The PC 1 comprises an image transmitter control means 6 for controlling the operation of the PC 1, based on connection request data sent from the receiver 2 and requesting connection to the PC 1 sent from the receiver 2; and a storage means 12 for storing images for sending to the receiver 2. The image transmitter control means 6 establishes the connection to the receiver 2 sent the connection request data, when the connection request data is recognized by a connection request data recognition section 7. A sending means 5 sends an image data file read by a file operation section 9 to the receiver 2. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种系统，通过该系统将视频数据从PC（视频发射机）1发送到接收机并被再现，而不提供向PC提供操作指令的外部输入装置在由存储视频数据的PC 1和接收视频数据的接收机2组成的系统中，根据接收机的功能，提供PC 1可以发送视频数据的系统。解决方案：PC1包括：图像发送器控制装置6，用于根据从接收机2发送的连接请求数据和请求从接收机2发送的PC 1的连接来控制PC1的操作; 以及存储装置12，用于存储用于发送到接收机2的图像。当连接请求数据识别部分7识别出连接请求数据时，图像发送器控制装置6建立与发送连接请求数据的接收机2的连接。发送装置5将由文件操作部分9读取的图像数据文件发送给接收机2.版权所有（C）2005，JPO＆NCIPI

58. 发明专利

JP2004147354A Cdma transmitter and cdma transmission method for the same 有权
标题翻译： CDMA发射机和CDMA发射方法
公开(公告)号：JP2004147354A
公开(公告)日：2004-05-20
申请号：JP2004021831
申请日：2004-01-29
申请人： Koninkl Philips Electronics Nv , コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人： PANZER HERBERT
IPC分类号： H04B1/04 , H04B1/707 , H04B7/26 , H04J3/18 , H04J13/00 , H04J13/10 , H04Q7/22 , H04Q7/38
CPC分类号： H04J3/18 , H04B1/707 , H04B7/2618 , H04B7/264 , H04J13/00 , H04J13/16
摘要： PROBLEM TO BE SOLVED: To provide a CDMA transmitter capable of making a system extremely flexible, and a CDMA transmission method for the same.
SOLUTION: The CDMA transmitter is provided with a means 11 for forming a frame structure, a means 12 for spreading data by using a code sequence according to spread coefficients depending on original payload data rates respectively, and means 10, 11 for compressing a data block to generate a burst with the compressed data. The means 10, 11 generate time periods in frames of of the frame structure not used for transmission of the compressed data blocks.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供能够使系统非常灵活的CDMA发射机以及用于其的CDMA发送方法。解决方案：CDMA发射机设置有用于形成帧结构的装置11，用于通过分别根据原始有效载荷数据速率根据扩展系数使用码序列扩展数据的装置12和用于压缩的装置10,11 用于产生具有压缩数据的突发的数据块。装置10,11在不用于传送压缩数据块的帧结构的帧中生成时间段。版权所有（C）2004，JPO

59. 发明专利

JPH11331264A EFFICIENT COMMUNICATION METHOD AND EQUIPMENT USING PAGE REGISTER 失效
公开(公告)号：JPH11331264A
公开(公告)日：1999-11-30
申请号：JP7488899
申请日：1999-03-19
申请人： HEWLETT PACKARD CO
发明人： DEBENDORA DAS SHARUMA
IPC分类号： H04L29/08 , H04J3/18 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To expand band width without increasing frequency or the number of wires by providing a means or the like for referring to the position of one bit pattern stored in an information packet instead of one bit pattern at a transmission side node for transmitting the information packet. SOLUTION: A network system 10 is provided with two nodes A 11 and B 12 connected by a bus 13. Then, the transmission side node A 11 for transmitting the information packet to the reception side node B 12 dynamically judges whether at least one bit pattern in the information packet is repeated in the following information packet or not (a), stores one bit pattern when the repetition of one bit pattern is discriminated by the dynamic determining means (b) and further refers to the position of one bit pattern stored in the information packet instead of one bit pattern (c).

60. 发明专利

JP2641916B2 失效
公开(公告)号：JP2641916B2
公开(公告)日：1997-08-20
申请号：JP22399488
申请日：1988-09-07
申请人： NIPPON DENKI KK
发明人： NAKANISHI TADASHI
IPC分类号： G10L19/00 , H04B14/04 , H04J3/18

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