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    • 51. 发明专利
    • Analog/digital conversion circuit
    • 模拟/数字转换电路
    • JP2007214959A
    • 2007-08-23
    • JP2006033594
    • 2006-02-10
    • Oki Electric Ind Co LtdOki Micro Design Co Ltd株式会社 沖マイクロデザイン沖電気工業株式会社
    • YAMADA TOSHIMI
    • H03M1/56
    • H03M1/123
    • PROBLEM TO BE SOLVED: To provide a multi-input A/D conversion circuit by which a conversion time is shortened without increasing a layout area and current consumption.
      SOLUTION: When the most significant bit b8 of a binary counter 30 is "L", each input signal INi is sampled by a sample-and-hold part 10 and digital signals Di held in each data holding part 50
      i are sequentially selected by a selector 60 and outputted. When the most significant bit b8 becomes "H", each input signal INi is held as analog signals Ai and compared with reference voltage REF generated according to digital signals DIG by a DAC 20. When a determination signal Ri outputted from a comparator changes from "L" to "H", the digital signal DIG at that time is held in each data holding part 50
      i as the digital signal Di.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种多输入A / D转换电路,通过该电路可以缩短转换时间,而不增加布局面积和电流消耗。 解决方案:当二进制计数器30的最高有效位b8为“L”时,每个输入信号INi由采样保持部分10采样,并且保持在每个数据保持部分50中的数字信号Di < i 由选择器60依次选择并输出。 当最高有效位b8变为“H”时,每个输入信号INi被保持为模拟信号Ai,并与DAC 20根据数字信号DIG产生的参考电压REF进行比较。当从比较器输出的确定信号R1从“ L“到”H“时,数字信号DIG被保持在每个数据保持部分50 i 中作为数字信号Di。 版权所有(C)2007,JPO&INPIT
    • 52. 发明专利
    • D/a converter, a/d converter and semiconductor device
    • D / A转换器,A / D转换器和半导体器件
    • JP2007088971A
    • 2007-04-05
    • JP2005277190
    • 2005-09-26
    • Sony Corpソニー株式会社
    • ASAYAMA TAKESHIFUKUSHIMA NORIYUKINITTA YOSHIKAZUMURAMATSU YOSHITOKUAMANO SEIKI
    • H03M1/68H03M1/56H03M1/74H04N5/335H04N5/357H04N5/374H04N5/378
    • H03M1/66H03M1/0863H03M1/123H03M1/34H03M1/56H03M1/664H03M1/687H03M1/745H03M1/747
    • PROBLEM TO BE SOLVED: To provide a D/A converter for suppressing generation of gridges due to reference signal for single-slope integration-type A/D conversion. SOLUTION: A low order bit control unit 330 performs a frequency-dividing operation, and selects a low-order current source cell 533 of a weighted current value by using a (1/2) k frequency-division clock. A high order bit control unit 340 successively changes the shift output of each shift register in a shift register part 342 to an H level, by using a predetermined frequency-division clock to be generated by the frequency-dividing operation of the low order bit control unit 330 as a shift clock, and successively selects a high-level current source cell 355 of the same weighted currents by using the shift output. The low-order bit control unit 330 and the high-order bit control unit 340 are made to perform not independent operations but rather interlinked operations, and the high-order bit control unit 340 is able to surely select a current source cell corresponding to the next bit data, and to suppress generation of gridges. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种用于抑制由于单斜率积分型A / D转换的参考信号而产生栅格的D / A转换器。 解决方案:低位位控制单元330执行分频操作,并使用(1/2) k 选择加权电流值的低阶电流源单元533, 频分时钟。 高阶位控制单元340通过使用由低位比特控制的分频操作产生的预定分频时钟,将移位寄存器部分342中的每个移位寄存器的移位输出连续地改变为H电平 单元330作为移位时钟,并且通过使用移位输出连续地选择相同加权电流的高电平电流源单元355。 使低位比特控制单元330和高位比特控制单元340不执行独立操作,而是执行互连操作,并且高阶比特控制单元340能够可靠地选择对应于 下一个位数据,并抑制栅格的生成。 版权所有(C)2007,JPO&INPIT
    • 55. 发明专利
    • Data collecting circuit
    • 数据采集​​电路
    • JPS59212021A
    • 1984-11-30
    • JP8575783
    • 1983-05-18
    • Hitachi LtdHitachi Medical Corp
    • MAIO KENJIMORIYA ATSUSHI
    • H03M1/56A61B6/03G01N23/04G06F3/05G06F17/40H03M1/36
    • H03M1/123H03M1/56
    • PURPOSE:To obtain an inexpensive and high-S/N data collecting circuit by using a reference ramp function in common to all channels. CONSTITUTION:Respective counters K1-Kn start counting and the level of the ramp function is increased; when the level exceeds output levels V1-Vn of respective signal channels successively, outputs of comparators C1-Cn are inverted to 0 and a clock is not inputted from the counter Kn to the counter K1. Clocks corresponding to differences between the levels V1-Vn and a reference voltage VL remain in the counters K1-Kn. For the purpose, one ramp function generator 10 is provided, and a comparator, gate, and counter are installed for every channel; this simple constitution digitizes analog input signals of all the channels and performs A/D conversion over all the channel within a single ramp generation period to speed up the operation.
    • 目的:通过使用所有通道的共同参考斜坡功能来获得廉价和高S / N数据采集电路。 构成:各个计数器K1-Kn开始计数,斜坡功能的电平增加; 当电平连续地超过各个信号通道的输出电平V1-Vn时,比较器C1-Cn的输出反相为0,并且不从计数器Kn向计数器K1输入时钟。 对应于电平V1-Vn和参考电压VL之间的差异的时钟保留在计数器K1-Kn中。 为此,提供一个斜坡函数发生器10,并且为每个通道安装比较器,门和计数器; 这种简单的结构对所有通道的模拟输入信号进行数字化,并在单个斜坡发生时段内对所有通道执行A / D转换,以加速操作。