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51. 发明专利

JPS641256A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS641256A
公开(公告)日：1989-01-05
申请号：JP15705287
申请日：1987-06-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： OGAWA IKUO
IPC分类号： H01L21/768 , H01L21/316
摘要： PURPOSE:To easily flatten an interlayer insulating film by coating a layer formed in a previous step with silicon compound dissolved in an organic solvent, evaporating the solvent, and then lamp annealing it at a high temperature for a short time to form a coated oxide film as part or all of the insulating film. CONSTITUTION:A wiring layer 2 is formed on a silicon substrate 1 formed with a CVD oxide film 3, and an insulating layer 4 covering the film 3 and the layer 2 is then formed. Then, after the layer 4 is coated with silanol 7 dissolved in an organic solvent, the solvent is evaporated at 900 deg.C or lower in an electric furnace, and it is baked to a coating oxide film 7' by lamp annealing at 1000 deg.C or higher. Thereafter, an oxide film which contains both boron and phosphorus or one of them is formed on the film 7' by a CVD method, and the layer 5 is further flattened on its surface by H2/O2 oxidation. A wiring layer 6 is formed on the layer 5, and an interlayer insulating film 8 in which the film 7' is interposed between the layers 4 and 5 is formed. Thus, an interlayer insulating film having preferable flatness and etching resistance can be formed.

52. 发明专利

JPS63221642A WIRING STRUCTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63221642A
公开(公告)日：1988-09-14
申请号：JP5590487
申请日：1987-03-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO SHINICHI , HIRAYAMA MAKOTO , NAGATOMO MASAO , OGAWA IKUO , ONO YOSHIKAZU , FUJINAGA MASATO
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108
摘要： PURPOSE:To decrease a capacity without changing a wiring resistance of bit lines or the like, by forming wirings on conductors through two layer structure insulating films such as an upper layer insulating film and a lower layer insulating film and forming cross-sectional areas of these wirings into T shapes to the conductors. CONSTITUTION:An insulating film 2, an electrode layer 3, and a layer insulating film 4 are piled in order on a semiconductor substrate 1, and further bit lines 6 made of aluminium are formed thereon, and next the whole of its periphery is covered with an upper layer insulating film 5. Since the cross-sectional areas of the bit lines 6 are formed into T shapes, capacities on the upper layer part and on the lower layer part are generated independently. When a distance between the bit lines is sufficiently large, a width of the T-shaped upper layer part is more enlarged so that the capacity can be decreased effectively by combining a dielectric constant of the upper layer insulating film 5. Word lines in stead of the bit lines, and further general wirings are applicable for the signal lines. Polycrystal silicon, and high melting point metal, or high melting point metal silicide are usable, or two-layer structure of polycrystal silicon and high melting point metal or high melting point metal silicide is also usable.

53. 发明专利

JPS63160359A ELECTRIC WIRING STRUCTURE 失效
公开(公告)号：JPS63160359A
公开(公告)日：1988-07-04
申请号：JP30981186
申请日：1986-12-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： FUJINAGA MASATO , SATO SHINICHI , NAGATOMO MASAO , OGAWA IKUO , ONO YOSHIKAZU , HIRAYAMA MAKOTO
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To obtain an electric wiring structure which can shorten the delay time without changing the cross-sectional area in such a way that the cross-sectional shape of a conductor is made circular. CONSTITUTION:A conductor 2 having a circular cross section is buried in an insulator 3 which is composed of, e.g., silicon oxide, silicon nitride or the like and which is formed on a substrate 1 composed of silicon. Even with the same operation and function as those of a conventional structure, the delay time is shortened. This means that, when the cross-sectional area is definite, the surface area of the conductor having the circular cross section is smaller than that of the conductor having a rectangular cross section. That is to say, this means that the delay time of the conductor having the circular cross section can be made shorter than that of the conductor having the rectangular cross section. If the resistance of the conductor 2 is R (OMEGA) and the capacitance between the conductor 2 and the substrate 1 is CB (F), the delay time tau can be given by tau=R.CB (sec). A device becomes excellent with the shortening of the delay time tau.

54. 发明专利

JPS62202522A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62202522A
公开(公告)日：1987-09-07
申请号：JP4464386
申请日：1986-02-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： OGAWA IKUO , NAKAO SHUJI , FUJINAGA MASATO , HOSONO KUNIHIRO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/822 , H01L27/04
摘要： PURPOSE:To form a sputtering deposit layer containing an impurity element onto the side surface of a groove, and to shape an impurity diffusion layer having excellent controllability onto the side surface of the groove through subsequent heat treatment by a method wherein the groove is formed at the required position of a semiconductor device, the impurity element is implanted into the bottom of the groove, an impurity implanting layer is shaped and the impurity implanting layer is sputtered by an inert gas. CONSTITUTION:An silicon substrate 1 is reactive-ion etched, using an oxide film 2 as a mask to form a groove 3, and an impurity element, such as phosphorus, boron, etc., required for shaping an impurity diffusion layer is implanted into the silicon substrate 1 through an ion implantation method to form an impurity implanted layer 4. The impurity implanted layer 4 on the bottom of the groove 3 is sputtered by employing an inert gas, and an silicon layer containing the impurity element is deposited on the side surface section of the groove 3 as a sputtering deposit layer 5. Lastly, the impurity element is diffused through heat treatment to form an impurity diffusion layer 6 on the bottom and side surface section of the groove 3.

55. 发明专利

JPS6261358A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6261358A
公开(公告)日：1987-03-18
申请号：JP20100985
申请日：1985-09-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKAMOTO TATSURO , OGAWA IKUO
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/41
摘要： PURPOSE:To prevent silicon from being deposited on the boundary between a silicon substrate and electrodes in an element which uses a BPSG film as the second insulating film by forming the first metal film as barrier metal, and then using aluminum containing silicon as the second wiring metal film. CONSTITUTION:A silicon oxide film 3 is formed by thermally oxidizing on the main surface of a silicon substrate 1, a silicon oxide film BPSG4 which contains phosphorus and silicon is formed thereon, and a contacting hole 7 is then selectively formed to form an impurity diffused layer 2. Then, any of titanium-tungsten alloy, tungsten, titanium nitride, tantalum nitride, molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, and polysilicon films is formed by a sputtering method or a CVD method as the first metal film 5. Eventually, aluminum containing silicon, aluminum-silicon-copper alloy or a sole aluminum film is formed by a sputtering method or a CVD method as the second metal film 6, and heat treated to sinter the metal film.

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