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51. 发明专利

JPS61275966A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS61275966A
公开(公告)日：1986-12-06
申请号：JP11758685
申请日：1985-05-30
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： G06F15/16 , G06F12/00 , G06F13/18 , G06F15/173 , G06F15/177
摘要： PURPOSE:To efficiently reduce an over head of an access to a shared memory from respective microprocessors by fetching the data in the shared memory while operating by a program in an internal memory and communicating with other processor and carrying out a processing or the like such as a calculation and an output processing. CONSTITUTION:A microprocessor 1 outputs an address and the data on a local bus 13 in order to write the data to a shared memory 11 and a bus control circuit 3 holds the address in an address holding circuit 6 and the data in a write data holding circuit 5. The microprocessor 1 terminates a bus cycle and moves to a next operation. The bus control circuit 3 obtains an using right of a system bus 12 and outputs the address held in the address holding circuit 6 and the data held in the write data holding circuit 5 to a system data bus 17. The shared memory 11 receives the address and then writes the data in a relevant address of the shared memory 11 and returns a SACK 20.

52. 发明专利

JPS6152768A Interrupt control mechanism of multiprocessor system 失效
标题翻译：多处理器系统的中断控制机制
公开(公告)号：JPS6152768A
公开(公告)日：1986-03-15
申请号：JP17330284
申请日：1984-08-22
申请人： Hitachi Ltd
发明人： TANAKA HIROYUKI
IPC分类号： G06F9/46 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F15/17
摘要： PURPOSE:To improve execution efficiency of a system by accessing various peripheral equipment control devices (IOCE) by individual exclusive-use processors respectively and directly. CONSTITUTION:A processor 3X1 (x is 0 or 1.) has an interrupt multiplexer 3X3 and an interrupt mask circuit 3X2, and when a processor 301 starts IOCE321, the processor sends a command issuer identifier to IOCE321 together with a command. IOCE321 stores it to a command register 323 and a processor identifying register 322. After IOCE321 execute a command by the command executing circuit 326, an interrupt signal 324 is generated. The interrupt signal 324 selects an interrupt request line 305 from the processor identifier register 322 by a demultiplexer 325 and asserts an interrupt request. The processor 301 selects the interrupt request line 305 and therefore, it is transferred as an internal interrupt signal 304 and shifted to interrupt processing.
摘要翻译：目的：通过各个独立处理器直接访问各种外围设备控制设备（IOCE）来提高系统的执行效率。构成：处理器3X1（x为0或1）具有中断多路复用器3X3和中断屏蔽电路3X2，当处理器301启动IOCE321时，处理器与命令一起向IOCE321发送命令发放者标识符。 IOCE321将其存储到命令寄存器323和处理器识别寄存器322.在IOCE321执行命令执行电路326的命令之后，产生中断信号324。中断信号324由解复用器325从处理器标识符寄存器322中选择中断请求线305，并断言中断请求。处理器301选择中断请求线305，因此它被作为内部中断信号304传送并转移到中断处理。

53. 发明专利

JPS60167051A STORAGE DEVICE 失效
公开(公告)号：JPS60167051A
公开(公告)日：1985-08-30
申请号：JP2269484
申请日：1984-02-09
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： G06F12/16
摘要： PURPOSE:To use more data as readout data by writing the same data as data of all blocks during writing operation, reading data, block by block, individually during reading operation, and comparing data of plural blocks, bit by bit. CONSTITUTION:A low-order address 105 is inputted to memory blocks 101-103 to address of a memory cell. A high-order address, on the other hand, is inputted to a decoder circuit 107. A decoder circuit 107 inputs signals from a mode selection switch 109 and a memory area specifying switch 108 and outputs selection signals CS0-CS2 for the respective blocks according to a truth table. The memory blocks selected with the CS0-CS2 are written and read. Two blocks are written and read at the same time in mode I and data are compared during the reading to detect a memory readout error. Further, three blocks are written and read at the same time in mode II and a majority decision on read data is made to secure data against an error of one memory block.

54. 发明专利

JPS60103395A SIMULTANEOUSLY WRITABLE DISPLAY RAM CIRCUIT 失效
公开(公告)号：JPS60103395A
公开(公告)日：1985-06-07
申请号：JP21086783
申请日：1983-11-11
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： G09G5/02 , G09G1/28

55. 发明专利

JPS5836046A DATA HIGHWAY 失效
公开(公告)号：JPS5836046A
公开(公告)日：1983-03-02
申请号：JP13279181
申请日：1981-08-26
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： H04B3/46 , G06F13/00 , H04L12/437
摘要： PURPOSE:To obtain a data highway suitable for dual-system mutual backup by utilizing both doubled circuits in normal operation, and also obtaining a throughput as great as a single system if a circuit has a partial fault. CONSTITUTION:A station having an add-numbered address receives a signal only from a loop transmission line 120, and transmits the signal to even-numbered address stations through a communication control circuit 111, a modulating circuit 109, and a loop transmission line 119, and to even-numbered address stations through a communication control circuit 112, a modulating circuit 110, and a loop transmission line 120. If the station connected on the left-hand side in the station figure has a fault, a time-out detector 114 operates to set a time- out FF116. The output of the circuit 110 is sent to the transmission line 119 through an AND circuit 2, an OR circuit OR1, a demodulating circuit 107, the circuit 111, and the circuit 109. Therefore, the signal arriving through the transmission line 120 is sent back to the transmission line 119 by this station as a returning point.

56. 发明专利

JPS5746394A Data rom mounting method 失效
标题翻译：数据ROM安装方法
公开(公告)号：JPS5746394A
公开(公告)日：1982-03-16
申请号：JP12239780
申请日：1980-09-05
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： TANAKA HIROYUKI , KOIKE HIDEYUKI
IPC分类号： G06F9/06 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To facilitate an easy exchange of an ROM, by providing a pair of spare and using ROM sockets storing the station data to a front panel, and a changeover switch and a switching circuit. CONSTITUTION:In case a change is given to the station data, etc. and the contents of a using ROM1 has to be changed, a spare ROM2 is mounted on a front panel 14. Then a switch SW is turned toward the spare side, and accordingly NAND gates 7 and 8 open to set a filip-flop 9. As a result, a transistor (TR)13 is turned on to apply the power supply to the ROM2. On the contrary, a TR12 is turned off to break the power supply of the ROM1. Furthermore tri-state buffers 5 and 6 are turned on; while tri-state buffers 3 and 4 are turned off. Thus the separation of the ROM1 is made possible.
摘要翻译：目的：为了便于更换ROM，通过向前面板提供一对备用和使用的存储站数据的ROM插槽，以及切换开关和切换电路。构成：如果对站数据等进行了更改，并且必须改变使用ROM1的内容，则在前面板14上安装备用ROM2。然后将开关SW转向备用侧，并且因此，与非门7和8打开以设置一个写法器9.结果，晶体管（TR）13导通以将电源施加到ROM2。相反，TR12关闭以断开ROM1的电源。此外，三态缓冲器5和6接通; 而三态缓冲器3和4被关闭。因此，ROM1的分离成为可能。

57. 发明专利

JPS5413228A INTERFACE CIRCUIT OF AUXILIARY MEMORY UNIT 失效
公开(公告)号：JPS5413228A
公开(公告)日：1979-01-31
申请号：JP7784277
申请日：1977-07-01
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： G06F12/16 , G11C29/00
摘要： PURPOSE:To obtain the information of error data, by providing the buffer memory memorizing the address of the error data through reading out from the control register and by reading out this memory content after the end of data transfer.

58. 发明专利

JPS54537A DETECTOR FOR CLOCK DOWN OF STATION 失效
公开(公告)号：JPS54537A
公开(公告)日：1979-01-05
申请号：JP6476777
申请日：1977-06-03
申请人： HITACHI LTD
发明人： TANAKA HIROYUKI
IPC分类号： G06F11/00 , G06F1/04 , G06F3/00 , G06F11/30 , G06F13/00 , G06F15/16
摘要： PURPOSE:To detect most of the failures in the station itself and to avoid the malfunctions due to the failures in the preceding station, by setting the out time of one of the clock down time out circuits.

59. 发明专利

JP2010016081A Cryogenic storage container and cryogenic apparatus 有权
标题翻译：低温储存容器和低温装置
公开(公告)号：JP2010016081A
公开(公告)日：2010-01-21
申请号：JP2008173190
申请日：2008-07-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAGIYA ISAO , TANAKA HIROYUKI , NEMOTO TAKEO , SAHO NORIHIDE
IPC分类号： H01L39/04 , F25B9/00 , H01F6/00 , H01F6/04
CPC分类号： F25D19/00 , H01F6/04
摘要： PROBLEM TO BE SOLVED: To provide a cryogenic storage container that maintains a cryogenic temperature for many hours when a running of a refrigerator stops as well. SOLUTION: The cryogenic storage container 10A has such a structure as to accommodate a solid coolant tub 12 for storing a solid coolant cooled by a refrigerator 25, and a liquid coolant tub 21 disposed so as to surround an outer periphery of the solid coolant tub 12 at fixed intervals for receiving a liquid coolant, inside a vacuum container 11. Further, with this structure, when the refrigerator 25 is stopped, the liquid coolant generating in the solid coolant tub 12 spontaneously flows into the liquid coolant tub 21 by a melting of the solid coolant, and a radiant invasive heat from the vacuum container 11 is consumed as a latent heat of vaporization of the liquid coolant in the liquid coolant tub 21. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在冰箱运行也停止时保持低温温度许多小时的低温储存容器。解决方案：低温储存容器10A具有这样的结构：容纳用于储存由冰箱25冷却的固体冷却剂的固体冷却剂桶12和设置成包围固体外周的液体冷却剂桶21 另外，利用这种结构，当冰箱25停止时，在固体冷却剂桶12中产生的液体冷却剂通过下述方式自发地流入液体冷却剂桶21：固体冷却剂的熔化和来自真空容器11的辐射入侵的热量被消耗作为液体冷却剂桶21中的液体冷却剂的蒸发潜热。（C）2010，JPO＆INPIT

60. 发明专利

JP2009134397A Computer and method for controlling whether or not to release all real storage areas assigned to virtual volume 审中-公开
标题翻译：控制无论是否释放所有实际存储区域的计算机和方法分配给虚拟体积
公开(公告)号：JP2009134397A
公开(公告)日：2009-06-18
申请号：JP2007308417
申请日：2007-11-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA HIROYUKI
IPC分类号： G06F12/00 , G06F3/06 , G06F13/10
CPC分类号： G06F3/0631 , G06F3/0613 , G06F3/0617 , G06F3/067
摘要： PROBLEM TO BE SOLVED: To prevent a drop in the access performance and also to prevent a shortage of unassigned real storage areas.
SOLUTION: A management server 111 performs a release/non-release selection determining whether or not to release all of the real storage areas assigned to a virtual volume 125V switched from a use target to an unused target. The management server exercises control to determine whether or not to release all of the real storage areas assigned to the specified virtual volume in accordance with the result of the release/non-release selection.
COPYRIGHT: (C)2009,JPO&INPIT

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