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1. 发明专利

JP5756876B2 ワンタイムプログラマブル機能を有するメモリ装置有权
标题翻译：具有一次性可编程功能存储器设备
公开(公告)号：JP5756876B2
公开(公告)日：2015-07-29
申请号：JP2014081321
申请日：2014-04-10
申请人：マグナチップセミコンダクター有限会社 , MAGNACHIP SEMICONDUCTOR LTD
发明人：シンチャンヒ , チョギソク , オグォンヨン
IPC分类号： G11C17/14
CPC分类号： G09G3/36 , G09G3/3696 , G11C17/00 , G11C17/16 , G11C5/145 , G11C5/147 , G11C7/02 , G09G2300/0426

2. 发明专利

JP5524508B2 Display device 有权
公开(公告)号：JP5524508B2
公开(公告)日：2014-06-18
申请号：JP2009113278
申请日：2009-05-08
申请人：マグナチップセミコンダクター有限会社Magnachip Semiconductor Ltd
发明人：チャンヒシン , ギソクチョ , グォンヨンオ
IPC分类号： G09F9/30 , G02F1/133 , G02F1/1345 , G09F9/00 , G09G3/20 , G09G3/36 , G11C16/06
CPC分类号： G09G3/36 , G09G3/3696 , G09G2300/0426 , G11C5/145 , G11C5/147 , G11C7/02 , G11C17/00 , G11C17/16

3. 发明专利

JP2009276764A Memory device having one time programmable function, driving chip for display panel provided with the same and display device 有权
标题翻译：具有一次可编程功能的存储器件，为其显示面板提供驱动芯片和显示器件
公开(公告)号：JP2009276764A
公开(公告)日：2009-11-26
申请号：JP2009113278
申请日：2009-05-08
申请人： Magnachip Semiconductor Ltd , マグナチップセミコンダクター有限会社Magnachip Semiconductor Ltd
发明人： SHIN CHANG-HEE , CHO KI-SEOK , OH KWON-YOUNG
IPC分类号： G09F9/30 , G02F1/133 , G02F1/1345 , G09F9/00 , G09G3/20 , G09G3/36 , G11C16/06
CPC分类号： G09G3/36 , G09G3/3696 , G09G2300/0426 , G11C5/145 , G11C5/147 , G11C7/02 , G11C17/00 , G11C17/16
摘要： PROBLEM TO BE SOLVED: To provide a driving chip for a display panel which is not affected by the noise attributed to a pad for a writing voltage of OTP (one time programmable) in a driving chip for a display panel provided with an OTP function.
SOLUTION: This is a driving chip for a display panel in which an inside voltage generation part which generates an inside voltage on receiving the input of an outside voltage and a memory device having an OTP function are built-in. The driving chip for a display device is provided in which the memory device is connected with the inside voltage generation part via a first inside wiring so that the memory device operates by the inside voltage generated from the inside voltage generation part in writing in operation on receiving an input at the writing voltage.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于显示面板的驱动芯片，其不受由用于显示面板的驱动芯片中的OTP（一次可编程）的写入电压的归因于焊盘的噪声的影响， OTP功能。解决方案：这是用于显示面板的驱动芯片，其中内置了在接收到外部电压的输入时产生内部电压的内部电压产生部分和具有OTP功能的存储器件。提供了一种用于显示装置的驱动芯片，其中存储器件经由第一内部布线与内部电压产生部分连接，使得存储器件在接收时在操作中以内部电压产生部分产生的内部电压进行操作在写入电压下的输入。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2004031904A Memory cell 审中-公开
公开(公告)号：JP2004031904A
公开(公告)日：2004-01-29
申请号：JP2003050503
申请日：2003-02-27
申请人： Hewlett Packard Co , ヒューレット・パッカード・カンパニーHewlett−Packard Company
发明人： FRICKE PETER , VAN BROCKLIN ANDREW L , ANDERSON DARYL
IPC分类号： G11C17/00 , G11C17/06 , G11C17/14 , G11C17/16 , G11C17/18 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C17/18 , G11C17/00 , G11C17/06 , G11C17/16
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory circuit in which a memory storage capacity is improved with a small occupying space and which can be inexpensively manufactured. SOLUTION: A memory device includes a memory component constituted to display a logical value corresponding to a data bit in a bit sequence and having an initial first resistance, a fault memory component constituted to display a second logical value corresponding to data bit in a bit sequence, and an additional memory component constituted to display an encoded bit in a bit sequence relating to the bit sequence with the fault memory component. The additional memory component is constituted to display an encoded bit showing whether the logical state of each data bit in the bit sequence is inverted or not. COPYRIGHT: (C)2004,JPO

5. 发明专利

JPS613037B2 JPS613037B2 - 失效
公开(公告)号：JPS613037B2
公开(公告)日：1986-01-29
申请号：JP3751384
申请日：1984-02-29
申请人： Tokyo Shibaura Electric Co
发明人： ASANO MASAMICHI , IWAHASHI HIROSHI
IPC分类号： G11C16/06 , G11C17/00
CPC分类号： G11C17/00

6. 发明专利

JPS60211699A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS60211699A
公开(公告)日：1985-10-24
申请号：JP6769384
申请日：1984-04-06
申请人： Hitachi Ltd
发明人： KURODA KENICHI
IPC分类号： G11C16/06 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To improve read/write characteristics of an EPROM by impressing a grounding potential and a substrate backup bias voltage in accordance with selection and non-selection of a floating gate/avalache injection MOSFET(FAMOS) of an element forming area. CONSTITUTION:When FAMOSQ11-Q1n of an element forming area of a memory array M-ARY are selected through, for instance, a word line WL1, etc., an FETQ2 of a switch circuit S1 is turned on, and a substrate back bias voltage is supplied to the element forming area from a substrate back bias voltage generator circuit VBB-G. Conversely, when they are not selected, an FETQ1 is turned on, and a grounding voltage is supplied, whereby relative threshold voltages of the FAMOSQ11-Q1n change in accordance with the selection and non-selection. Consequently, a conductance characteristic of the FAMOS where writing is carried out at the time of writing becomes larger, and most parts of a write current blow, which causes a leak current to the non-selected FAMOS to be reduced. This can apply reading, and write/read characteristics of an EPROM can be improved.
摘要翻译：目的：通过根据元件形成区域的浮动栅极/ avalache注入MOSFET（FAMOS）的选择和不选择来施加接地电位和衬底备用偏置电压来提高EPROM的读/写特性。构成：当通过例如字线WL1等来选择存储器阵列M-ARY的元件形成区域的FAMOSQ11-Q1n时，开关电路S1的FETQ2导通，并且衬底背偏置电压从基板背偏压生成电路VBB-G供给到元件形成区域。相反，当它们未被选择时，FETQ1导通，并且提供接地电压，由此FAMOSQ11-Q1n的相对阈值电压根据选择和不选择而改变。因此，在写入时执行写入的FAMOS的电导特性变大，并且写入电流的大多数部分吹动，导致对未选择的FAMOS的漏电流减少。这可以应用于读取，并且可以提高EPROM的写入/读取特性。

7. 发明专利

JPS59191196A Nonvolatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：JPS59191196A
公开(公告)日：1984-10-30
申请号：JP6533183
申请日：1983-04-15
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： NABEYA SHINJI , SATOU NOBUYUKI
IPC分类号： G11C16/02 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To emancipate a user from troubles of time control and to make the device easy to handle by realizing the proper time for writing or erasing in each memory cell without compelling the user to perform troublesome time control. CONSTITUTION:A pulse generating circuit 32 is started by a controlling signal i.e. a program signal Po given from the outside for writing or erasing, and generates a pulse signal Pi of specified time width. An MOS transistor of floating gate structure is used in each memory cell that constitutes a memory matrix 10. In the case of floating gate structure, writing of storage data is made by accumulation of charge in the gate. Erasing is made by discharging accumulated charges of the gate. Accumulation of charges of the gate or discharging of charges from the gate is made in a gate writing circuit 24 or an erasing circuit 26 by using the high voltage generated in a writing/erasing voltage generating circuit 28.
摘要翻译：目的：解决用户从时间控制的麻烦，通过在每个存储单元中实现写入或擦除的适当时间，使设备易于处理，而不需要用户执行麻烦的时间控制。构成：通过控制信号（即从外部给出的编程信号Po）进行写入或擦除来启动脉冲发生电路32，并产生规定时间宽度的脉冲信号Pi。在构成存储矩阵10的每个存储单元中使用浮置栅极结构的MOS晶体管。在浮栅结构的情况下，通过栅极中的电荷积累来进行存储数据的写入。通过放电门的累积电荷进行擦除。通过使用在写入/擦除电压产生电路28中产生的高电压，在栅极写入电路24或擦除电路26中进行栅极充电的积累或从栅极放电。

8. 发明专利

JPS59154692A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS59154692A
公开(公告)日：1984-09-03
申请号：JP2877283
申请日：1983-02-23
申请人： Toshiba Corp , Tosubatsuku Service:Kk
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO
IPC分类号： G11C11/41 , G11C11/34 , G11C16/06 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To speed up data read speed by providing an MOS transister (TR) for discharging which discharges the charge on a data line coupled with plural memory cells so as to turn on an MOS TR7 when an address signal changes. CONSTITUTION:An MOS TR(Q)41 is connected between a circuit point S being an input terminal of a sense amplifier 36 and a reference potential point and an output signal from an NOR circuit 49 is inputted to its gate. Further, the output pulse from a pulse generating circuit 45 is inputted to the gate of a Q47 being a driving transistor to the NOR circuit 49 and the output signal from an inverter 44 is inputted to the gate of a Q48 being other driving TR respectively. Further, a signal at a connecting point between the Q46 and Q47, 48 in the NOR circuit 49 is inputted to the gate of the Q41 for discharge as an output signal in this circuit. A threshould voltage of said inverter 44 and a data sense level of the sense amplifier 36 are almost coincident with each other, then the discharge by the Q41 is attained in the vicinity of the sense level of the sense amplifier 36, thereby attaining the detection of data of the sense amplifier 36 in a short time.
摘要翻译：目的：通过提供放电的MOS转移器（TR）来加速数据读取速度，其中，在与多个存储单元耦合的数据线上放电，以便在地址信号改变时接通MOS TR7。构成：将MOS TR（Q）41连接在作为读出放大器36的输入端的电路点S与基准电位点之间，将来自NOR电路49的输出信号输入到其门。此外，来自脉冲发生电路45的输出脉冲被输入到NOR电路49的驱动晶体管的Q47的栅极，并且来自反相器44的输出信号分别输入到作为其他驱动TR的Q48的栅极。此外，在NOR电路49中的Q46与Q47,48之间的连接点处的信号作为该电路中的输出信号输入到用于放电的Q41的栅极。所述反相器44的检测电压和读出放大器36的数据感测电平几乎一致，则在读出放大器36的感测电平附近获得Q41的放电，从而实现检测在短时间内读出放大器36的数据。

9. 发明专利

JPS59140696A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59140696A
公开(公告)日：1984-08-13
申请号：JP1273883
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： MASUDA KENZOU , OOI EIJI
IPC分类号： G11C17/00 , G11C17/12
CPC分类号： G11C17/00
摘要： PURPOSE:To obtain a semiconductor integrated circuit device containing a vertical ROM which is capable of a high-speed reading action by providing a precharge circuit which receives a precharge signal and supplies a precharge level to a well region. CONSTITUTION:A precharge MOSFETQp1 or Qpn is connected between each serial MOSFET and a positive power supply voltage OV. The Qp1 or Qpn is turned on while a timing signal phip is kept at a low level to precharge each juncture between an output line and the serial MOSFET up to a high level (OV). In other words, the output voltage of an inverter IV is set at a high level to set a well region WL1 at a high level. Therefore a parasitic diode consisting of the region WL1 and an n region where the source and the drain of the serial MOSFET are formed is biased forward and turned on to transmit the above- mentioned high level to each source and drain. Thus the precharge is performed through said parasitic diode. This can extremely shorten the precharge time.
摘要翻译：目的：通过提供接收预充电信号并向井区提供预充电电平的预充电电路，获得能够进行高速读取动作的垂直ROM的半导体集成电路装置。构成：每个串联MOSFET和正电源电压OV之间连接一个预充电MOSFETQp1或Qpn。 Qp1或Qpn导通，同时定时信号phip保持在低电平，以便在输出线和串联MOSFET之间的每个接合点预充电达高电平（OV）。换句话说，将逆变器IV的输出电压设定为高电平，将阱区域WL1设定为高电平。因此，由形成串联MOSFET的源极和漏极的区域WL1和n +区组成的寄生二极管被向前偏置并导通，以将上述高电平传输到每个源极和漏极。因此，通过所述寄生二极管执行预充电。这可以极大地缩短预充电时间。

10. 发明专利

JPS59135699A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS59135699A
公开(公告)日：1984-08-03
申请号：JP726783
申请日：1983-01-21
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MOCHIZUKI MASAYOSHI , FUJIMOTO MICHIO
IPC分类号： G11C16/04 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To obtain an inexpensive programmable ROM impossible for rewrite with large storage capacity by using an FAMOS transistor (TR) and omitting its erasing function, in other words, using a plastic package or the like not having an erasing window. CONSTITUTION:An MOSFETQ1 is turned on by applying a high write voltage of about 24V to an external terminal Vpp. Thus, a high voltage of about 10V is applied to a drain of an MOSFETQ2. A normal write operation control signal is applied in this state and an output of an inverter IV1 shown in Fig. 2 goes to a low level by applying a high level signal of about 8V to an external terminal A1, an MOSFETQ4 is turned off and since an output of an inverter IV2 goes to a high level, an MOSFETQ10 is turned off by the low level of a gate control signal -we. Thus, a write selecting signal from a depletion type MOSFETQ15 is applied to a dummy word line DW.
摘要翻译：目的：通过使用FAMOS晶体管（TR）并省略其擦除功能，换句话说，使用没有擦除窗口的塑料封装等，获得不可能用大存储容量进行重写的便宜的可编程ROM。构成：通过向外部端子Vpp施加大约24V的高写入电压，MOSFETQ1导通。因此，大约10V的高电压被施加到MOSFET Q2的漏极。在该状态下施加正常写入操作控制信号，并且在图1所示的反相器IV1的输出端施加正常的写入操作控制信号。 2通过向外部端子A1施加约8V的高电平信号而变为低电平，MOSFETQ4截止，并且由于反相器IV2的输出变为高电平，所以MOSFETQ10被截止为低电平门控制信号-we。因此，来自耗尽型MOSFETQ15的写入选择信号被施加到虚拟字线DW。

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