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51. 发明专利

JPS5775029A Decoder 失效
标题翻译：解码器
公开(公告)号：JPS5775029A
公开(公告)日：1982-05-11
申请号：JP15075080
申请日：1980-10-29
申请人： Hitachi Ltd
发明人： SATOU HIDEHIRO , YAMAKIDO KAZUO
IPC分类号： H03M1/66 , H03M1/38 , H03M1/80 , H04B14/04
CPC分类号： H03M1/80
摘要： PURPOSE:To obtain a decoder having a prescribed nonlinearity, by setting the ratio of the overall capacity value of a capacitor array circuit to the capacity value of the hold capacitor of a sample holding circuit to a prescribed value. CONSTITUTION:A reset switch RS2 is closed to discharge a hold capacitor CH, and next, a set switch ST is connected to an input terminal VIN and a sampling switch SP is closed. An input voltage is divided and applied to capacitors C1- C8, and switches S1-S8 are controlled selectively by a PCM code. At this time, when the overall capacity value of capacitors C1-C8 is denoted as Ca, the gain of a sample holding circit is GSH= Ca/CH. Since Ca=256C is true, CH is 251C/alpha approximately in case of the mu rule and is 252C/alpha in case of the A rule. However, alpha is 1 practically.
摘要翻译：目的：通过将电容器阵列电路的总电容值与采样保持电路的保持电容的容量值的比例设定为规定值，来获得规定的非线性的解码器。构成：复位开关RS2闭合以放电保持电容CH，接下来，将一个开关ST连接到输入端VIN，并且采样开关SP闭合。输入电压被分压并施加到电容器C1-C8，开关S1-S8由PCM代码选择性地控制。此时，当电容器C1-C8的总容量值表示为Ca时，样品保持环路的增益为GSH = Ca / CH。由于Ca = 256℃是真的，在μ规则的情况下，CH约为251C /α，在A规则的情况下为252C /α。然而，alpha实际上是1。

52. 发明专利

JPS5616320A REFERENCE VOLTAGE SUPPLYING CIRCUIT 失效
公开(公告)号：JPS5616320A
公开(公告)日：1981-02-17
申请号：JP9156779
申请日：1979-07-20
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO
IPC分类号： H03M1/12 , G05F1/46 , G05F1/56 , H03K17/00 , H03M1/00
摘要： PURPOSE:To secure an equal absolute value for the output voltage switched to both the positive and negative directions, by providing the capacitor to compensate the floating capacity. CONSTITUTION:One end of capacitor C4 which compensates the floating capacity is connected to output terminal 11; and at the same time the other end is earthed via switch S6. And in the charging mode, switches S1, S2, S5 and S6 are turned on with other switches turned off respectively. Then capacitor C0 and floating capacitor C1 are charged with output voltage E of power source 6. In this instant, the charges of floating capacities C2 and C3 plus capacity C4 are all discharged. Then in the forward voltage output mode, switches S2, S3 and S6 are turned on with other switched turned off respectively. And the output given from terminal 12 is expressed by equation 2. Here if capacities C0 and C4 are set to satisfy equation 3, the absolute value can be made equal for the output voltage supplied from terminal 12.

53. 发明专利

JPS5496348A PCM DECODER CIRCUIT 失效
公开(公告)号：JPS5496348A
公开(公告)日：1979-07-30
申请号：JP279778
申请日：1978-01-17
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO , TSUKAMOTO NOBUO
IPC分类号： H03M1/66
摘要： PURPOSE:To secure the switching use between A-and mu-sides as well as between encoding and decoding by providing the encoding side switching terminal. CONSTITUTION:Circuit 8 is added to form -0.5muCP(inverse B5, B6, B7, and B8) in Eq. (1) which shows output level Dmu(m,n) based on A- and mu-sides switching logic circuit 7 and the mu-side (Circuit 8 is needed for the encoder at the mu-side and is not required substantially for the decoder). Along with circuit 8, circuit 9 is also provided to form (n p +np) of Eq. (1) and others. Circuit 7 consists of switch elements 71-73 plus logic elements 74-76 which are switched according to the A- side and mu-side. Polarity bit B1 and the lower 2-bit signals of BCD-t0-decimal decoder 6 are supplied to circuit 7 to deliver the signal to open and close 2-way switch S1 and S2 according to the A-side and mu-side.

54. 发明专利

JPS5257769A ANALOG SWITCH 失效
公开(公告)号：JPS5257769A
公开(公告)日：1977-05-12
申请号：JP13307175
申请日：1975-11-07
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO
IPC分类号： H03K17/687 , H03K17/04
摘要： PURPOSE:The diode and FET are connected as subscribed between source and gate of FET which gives signal current to load. Thus, a high-speed switching action becomes possible.

55. 发明专利

JPH09326786A SEMICONDUCTOR INTEGRATED CIRCUIT AND OPTICAL SIGNAL RECEIVER 失效
公开(公告)号：JPH09326786A
公开(公告)日：1997-12-16
申请号：JP14536596
申请日：1996-06-07
申请人： HITACHI LTD
发明人： YOSHIHARA KAZUHIRO , YAMAKIDO KAZUO
IPC分类号： G06F1/12 , H01L21/822 , H01L27/04 , H03K5/00 , H03K19/0175 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To adjust the phase of a clock signal to an optimum phase automatically by sampling data respectively at a phase lead point by a prescribed phase from a clock timing and at a phase lag point by a prescribed phase and comparing the results so as to change the absolute phase. SOLUTION: A clock signal CLK3 received via an input terminal P2 is fed to an FF 11 via a phase adjustment circuit 12. Furthermore, a data signal ED3 whose phase is to be compared with the phase of the signal CLK 3 is given to the circuit 12 as a signal ED3' via a data input buffer circuit 13. The FF 11 fetches data when a clock signal CK is in crossing with a center potential on the way of changing itself from an H to an L level as a sampling timing. Then the data fetched by the FF 11 are outputted as a signal ED3 from a data output buffer circuit 15. The circuit 12 compares the phase of the received data signal with the phase of the clock signal and provides the clock signal CK whose phase is adjusted to an optimum phase to the FF 11.

56. 发明专利

JPH07245534A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07245534A
公开(公告)日：1995-09-19
申请号：JP5668694
申请日：1994-03-02
申请人： HITACHI LTD
发明人： TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03F3/34
摘要： PURPOSE:To promote a low voltage supply and low power consumption for a portable communication terminal equipment or the like and to make the size small, to make the weight light and to reduce the cost by realizing a level shift circuit suitably interfacing circuits using different power supply voltages as operating power supply voltages. CONSTITUTION:In a portable communication terminal equipment or the like provided with plural circuits whose power supply voltages are different, that is, provided with LSIs, a level shift circuit LSFI interfacing the LSIs in which a center potential of an analog signal in each LSI is set respectively to half of power supply voltages VDD, VCC, is basically provided with an operational amplifier OA2 whose inverting input terminal (-) receives an input analog signal Vi via a resistor R1 and whose noninverting input terminal (+) receives a prescribed bias voltage VL and with a resistor R2 located between the inverting input terminal (-) and an output terminal of the amplifier OA2.

57. 发明专利

JPH06244656A DIFFERENTIAL SIGNAL PREPARING CIRCUIT 失效
公开(公告)号：JPH06244656A
公开(公告)日：1994-09-02
申请号：JP5518993
申请日：1993-02-19
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KUDO MASAKI , TANBA HIROKO , OKAZAKI TAKAO , YAMAKIDO KAZUO
IPC分类号： H03F3/45 , H03F3/34
摘要： PURPOSE:To reduce unwanted phase delay between differential signals with comparatively simple configuration and to reduce power consumption without requiring any complete differential arithmetic amplifying circuit or filter circuit for delay adjustment. CONSTITUTION:Mainly, the signals of mutually opposite phases are formed at VOUT 1 and VOUT 2 by a forward amplifying circuit AMP 1 and at inverse amplifying circuit AMP 2 respectively provided with differential steps, output steps and phase compensating capacitors, and the unwanted phase delay between the differential signals is reduced by using a means for equalizing gain band widths at the forward and inverse amplifying circuits by changing currents to flow to the phase compensating capacitors or the differential steps of both of amplifying circuits.

58. 发明专利

JPH06209263A A/D CONVERTER 失效
公开(公告)号：JPH06209263A
公开(公告)日：1994-07-26
申请号：JP324193
申请日：1993-01-12
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： WATANABE HIROBUMI , OKAZAKI TAKAO , KITA MASAHITO , YAMAKIDO KAZUO
IPC分类号： H03M1/36
摘要： PURPOSE:To enable the noise proofing property and low power consumption property of an A/D converter under the circumstance of low power supply voltage by stabilizing the reference voltage across a voltage divider resistor array constantly also when constant current in a voltage divider resistor array is reduced. CONSTITUTION:Voltage followers 51, 52 perform the negative feedback control of the source follower output voltage of MOSTr M1, M2 in arthmetic amplifiers AP1, AP2 so that the reference voltage VH, VL across a voltage divider resistor array 1 may be constant voltage. A voltage follower 6 transmits the voltage of an analog input signal Ain to each comparator CP of a comparator circuit column 2. At this time, the followers 51, 52 stabilizes the feedback operation in constant current circuits ICS1, ICS2 flowing very small constant current from the feedback input side of the amplifiers AP1, AP2. Thus, by compulsorily stabilizing the operation by the negative feedback control of the source followers of Tr M1, M2 and the amplifiers AP1, AP2, the voltage VH, VL across the voltage divider resistor array 1 can be always made constant even when the constant current of the resistance column 1 is small.

59. 发明专利

JPH0661859A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A/D CONVERSION CIRCUIT 失效
公开(公告)号：JPH0661859A
公开(公告)日：1994-03-04
申请号：JP23431192
申请日：1992-08-10
申请人： HITACHI LTD
发明人： TANBA HIROKO , YAMAKIDO KAZUO , OKAZAKI TAKAO , NISHIKAWA NORIMITSU , KOBAYASHI YOICHIRO
IPC分类号： H03M1/38 , H03F3/343 , H03F3/347 , H03M1/74
摘要： PURPOSE:To provide a current source with a high output impedance, a highly accurate current mirror circuit and an A/D conversion circuit with high accuracy and low power consumption. CONSTITUTION:A source of a MOS transistor(TR) M1 is connected to a power supply VDD and its gate receives a voltage VB1. The device is provided with the MOS TR M1, an operational amplifier 1 whose inverting input terminal connects to a drain of the MOS TRM1 and whose noninverting input terminal receives a voltage VB2, and a MOS TR M2 whose gate receives an output of the operational amplifier and whose source is connected to the drain of the TR M2, and they form a constant current source using the drain of the TR M2 as a current output terminal. A constant current flows to an imaginary ground of the operational amplifier without changing a drain voltage of the MOS TR M1 deciding the current even when a voltage at the current output terminal is subjected to change and then the current source with a high impedance is realized. A highly accurate current mirror is obtained by selecting drain voltages of the current mirror pair identically as an imaginary ground similarly to above.

60. 发明专利

JPH0563578A A/D CONVERTER 失效
公开(公告)号：JPH0563578A
公开(公告)日：1993-03-12
申请号：JP24827791
申请日：1991-09-02
申请人： HITACHI LTD
发明人： ISHIHARA HAYATO , TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03M3/02
摘要： PURPOSE:To prevent deterioration in the characteristic due to switching noise by eliminating the need for a sampling switch in a current drive type A/D converter. CONSTITUTION:The A/D converter is provided with a voltage/current conversion circuit 1, a local D/A converter circuit 2 whose output current is controlled by a digital signal, an output current difference to an analog circuit 3 whose one terminal connects to a DC potential point is integrated and a voltage resulting from the integration is quantized by a quantization circuit 4, the result is integrated by a digital integration circuit 5 and the integrated value is given to a feedback quantity correction circuit 6 and the result of A/D conversion is outputted. The feedback quantity correction circuit 6 applies correction to cancel an analog error sampled by the analog circuit 3 to the digital signal till the output of the quantization circuit 4 is reflected on an output of the local D/A converter circuit 2 (till digital integration is implemented to a quantization output).

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