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51. 发明专利

JPS5911589A Detector circuit for bubble memory 失效
标题翻译：用于爆破记忆的探测器电路
公开(公告)号：JPS5911589A
公开(公告)日：1984-01-21
申请号：JP11855482
申请日：1982-07-09
申请人： Hitachi Ltd
发明人： TOYOOKA TAKASHI , AOKI HIROKAZU , SUGIE MAMORU , SUGITA KEN
IPC分类号： G11C11/14 , G11C19/08
CPC分类号： G11C19/0866
摘要： PURPOSE: To eliminate the cause to level fluctuation, by adding a circuit setting a reference level discriminating 0, 1 of a detecting line signal in response to a detected output waveform, when only a reading signal corresponding to "0" is generated on the detecting line.
CONSTITUTION: An output CONT of a control circuit 23 is set to an L level at the beginning of a threshold level set period, and an output RESET pulse of the circuit 23 is inputted to a threshold level set circuit 22. As a result, an output VTH of the set circuit 22 is set to an initial value. This initial value is set to a minimum level or below taken by an output of a differential amplifier 10 corresponding to a reading signal corresponding to "0" information. Thus, an output COUT of a comparator 11 is at H without fail. The COUT is inputted to the set circuit 22 through a gate 25 to increase the level of the output VTH by Δv according to the pulse. When the same operation is executed for plural number of times with the VTH set newly, the VTH is increased more than the output of the differential amplifier 10. Since no COUT is outputted after that, the VTH is kept to a prescribed level. An SET pulse is inputted from the circuit 23 to the circuit 22 at the end of the threshold level set period to increase the output VTH of the set circuit 22 by a required set value Δv'. The threshold level VTH set with above-mentioned process is held and the next readout is executed.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了消除原因引起的电平波动，通过添加一个电路，设置一个参考电平，根据检测到的输出波形来区分检测线信号的0,1，而只有对应于“0”的读取信号产生检测线。构成：控制电路23的输出CONT在阈值电平设定周期的开始被设定为L电平，电路23的输出RESET脉冲被输入到阈值电平设定电路22.结果，设定电路22的输出VTH被设定为初始值。该初始值被设置为与对应于“0”信息的读取信号相对应的差分放大器10的输出所取得的最小电平或以下。因此，比较器11的输出COUT无故障地为H。 COUT通过门25输入到设置电路22，以根据脉冲增加输出VTH的电平DELTAv。当新的VTH设定相同的操作多次时，VTH比差分放大器10的输出增加得多。由于在此之后没有输出COUT，所以VTH保持在规定的水平。在阈值电平设定周期结束时，从电路23向电路22输入SET脉冲，将设定电路22的输出VTH增加所需设定值DELTAv'。保持用上述处理设定的阈值电平VTH，并执行下一个读出。

52. 发明专利

JPS5831459A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS5831459A
公开(公告)日：1983-02-24
申请号：JP12875981
申请日：1981-08-19
申请人： HITACHI LTD
发明人： SUGIE MAMORU , TOYOOKA TAKASHI , AOKI HIROKAZU , KAMIYAMA KAZUYA
IPC分类号： G11C11/14 , G06F3/00 , G06F12/06 , G06F13/18 , G06F13/30
摘要： PURPOSE:To flexibly correspond to a request of various data transfer speeds of an application system, by operating in parallel plural memory modules which have incorporated a controller and a clock generator, respectively. CONSTITUTION:Each memory module 9-1-9-n incorporates each controller 12-1- 12-n and each clock generator 13-1-13-n, and constitutes one complete memory itself. Also, a bus controlling circuit 10 controls data transfer based on direct memory access between a memory module which is operated asynchronuously, and a main memory 7, receives a data transfer request from each memory module, gives an approval to the memory module when conditions for transferring data have been arranged, and transfers the data between the main memory and the memory module.

53. 发明专利

JPS54134936A MAGNETIC BUBBLE DEVICE 失效
公开(公告)号：JPS54134936A
公开(公告)日：1979-10-19
申请号：JP4213278
申请日：1978-04-12
申请人： HITACHI LTD
发明人： YOSHIZAWA SHIGERU , AOKI HIROKAZU , CHIBA SHINSAKU , MAYAMA KOUICHI , TOYOOKA TAKASHI , SAITOU NOBUO
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To eliminate the level shift of a driving current by controlling an alternating current flowing to a driving coil so that when its waveform crosses the zero- value time axis, the time differentiation value of the waveform will be zero. CONSTITUTION:Direct-current voltage source 28 is connected across the parallel circuit, composed of the 1st series circuit of transistors 47 and 49 serving as the 1st and 2nd bothway switches and the 2nd series circuit of transistors 48 and 50 as the 3rd and 4th bothway switches, and driving coil 31 is also connected between connection points of transistors 47 and 49, and 48 and 50. Then, ON-OFF operations of transistors 47 to 50 are so controlled that there will be the time region where the time differentiation value of the waveform of an alternating current flowing through driving coil 31 is zero when the current changes from a positive value to a negative value and from a negative value to a positive value in terms of the time axis.

54. 发明专利

JPS5414636A MAGNETIC BUBBLE TRANSFER CIRCUIT OF CLOSED LOOP 失效
公开(公告)号：JPS5414636A
公开(公告)日：1979-02-03
申请号：JP7982577
申请日：1977-07-06
申请人： HITACHI LTD
发明人： HIROSHIMA MINORU , AOKI HIROKAZU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To establish the circuit excellent in transfer performance and to avoid malfunction at start and stop of rotating magnetic field, by providing the fourth element chip leading to near the soft ferromagnetic film of ''H'' pattern adjacent to other end.

55. 发明专利

JPH0685156B2 失效
公开(公告)号：JPH0685156B2
公开(公告)日：1994-10-26
申请号：JP11037385
申请日：1985-05-24
申请人： HITACHI LTD
发明人： TAKAGI KATSUAKI , AOKI HIROKAZU , NAKAGAWA NORIO , HAGIWARA YOSHIMUNE
IPC分类号： G06F12/08 , G06F12/10
摘要： An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

56. 发明专利

JPH04175948A INFORMATION PROCESSOR 失效
公开(公告)号：JPH04175948A
公开(公告)日：1992-06-23
申请号：JP30241990
申请日：1990-11-09
申请人： HITACHI LTD
发明人： NISHII OSAMU , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/08
摘要： PURPOSE:To enable invalidation control over a cache memory while suppressing an increase in the number of terminals without requiring any complicate control by inputting a signal of part of an address based upon one block of cache storage as one block to the cache memory and invalidating all blocks matching this address. CONSTITUTION:Processors 10 and 20 are equipped with inside caches 11 and 21 and outside caches 12 and 22. Then the signal of part of the address based upon one block of the cache memory as to a main storage address signal is inputted directly to caches 11, 12, 21, and 22 in one certain or plural layers and the cache memories 11, 12, 21, and 22 invalidate blocks matching the partial address in their storage parts. Consequently, while data are completely invalidated, the control is not made complicate and the number of external terminals of the internal caches 11 and 21 is never increased.

57. 发明专利

JPH04125760A BUS ARBITRATION SYSTEM 失效
公开(公告)号：JPH04125760A
公开(公告)日：1992-04-27
申请号：JP24664290
申请日：1990-09-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI TAKASHI , SAIKOU YASUHIKO , SASAKI KOTOKO , IWATA MASAKI , KUMAGAI TATSUHIKO , FURUNOMA TOSHIHIKO , HATANO SUSUMU , NISHIMOTO KENJI , AOKI HIROKAZU , UCHIYAMA KUNIO
IPC分类号： G06F15/16 , G06F13/362 , G06F13/374 , G06F15/177
摘要： PURPOSE:To accelerate an arbitration processing by arranging a logic circuit corresponding to a bus master to execute logical arithmetic between the wired OR result of priority order information between bus masters related to the request competition of a bus use right and the priority order information for each above-mentioned bus master. CONSTITUTION:When a bus request signal BREQ is asserted in another cache memory and the held contents of a register are loaded on a bus BAD exclusive for arbitration, the wired OR is obtained in the exclusive BAD. This wired OR result is inputted to an exclusive OR gate and exclusively ORed with the held value of a register 50 so as to be fetched into a size discrimination circuit 45. This result of size discrimination is delayed by a delay circuit 46, and a bus use right possessing signal BG is obtained.

58. 发明专利

JPH03219494A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03219494A
公开(公告)日：1991-09-26
申请号：JP1261090
申请日：1990-01-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HATANO SUSUMU , OOISHI KANJI , KIKUCHI TAKASHI , SAIE YASUHIKO , FUKUDA HIROSHI , UCHIYAMA KUNIO , AOKI HIROKAZU , NISHII OSAMU
IPC分类号： G11C11/417 , G11C11/413 , G11C29/00 , G11C29/42
摘要： PURPOSE:To attain acceleration and low power consumption by providing a switching means between a data line and an I/O device. CONSTITUTION:Switching transistors(TR) Q5, Q6-Q5', and Q6' are provided at each of a pair D0 of data lines, the inverse D0-DP, and the inverse DP, and the on and off of those transistors are controlled with a timing control signal DYC, and they are turned off when a static memory is read out and the amplifying operation of a sense amplifier SA0 is started. Thereby, the pair D0 of data lines to which a memory cell is connected is separated from the incidental capacitors of inverse D0..., and a load on a sense amplifier SW0 is reduced, which attains the acceleration of an operation and the low power consumption. Also, the same switching TRs Q24, Q25... of a column selector CS0 are turned on via a control signal Y0 until write data from the I/O device is held with the sense amplifier SA0.

59. 发明专利

JPH02213960A CACHE MEMORY 失效
公开(公告)号：JPH02213960A
公开(公告)日：1990-08-27
申请号：JP3484589
申请日：1989-02-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIKOU YASUHIKO , FUKUDA HIROSHI , KIKUCHI TAKASHI , FURUNOMA TOSHIHIKO , NAGASHIMA YASUSHI , UCHIYAMA KUNIO , AOKI HIROKAZU , NISHII OSAMU , OOISHI KANJI , KITANO JUN , HATANO SUSUMU
IPC分类号： G06F12/02 , G06F12/08
摘要： PURPOSE:To improve the system throughput by using a function which monitors the address change at the main memory side and changing automatically the store places of an internal address tag and/or data in accordance with the transfer address of the relevant data. CONSTITUTION:A function is prepared to monitor the address change at the main memory side and to automatically change the store places of an internal address tag and/or data in accordance with the transfer address of the relevant data. Thus the data on a cache memory can be effectively used even in the case where the store addresses are changed by a microprocessor MPU for the data on the dynamic relocation, the garbage collection, etc., against a main memory. As a result, the system throughput is improved.

60. 发明专利

JPH02122344A BUFFER MEMORY 失效
公开(公告)号：JPH02122344A
公开(公告)日：1990-05-10
申请号：JP27762488
申请日：1988-11-01
申请人： HITACHI LTD
发明人： SATO KATSUYUKI , NISHIMUKAI TADAHIKO , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/08 , G06F12/12 , G11C11/401
摘要： PURPOSE:To improve the function and the working speed of a cache memory by giving a partial writing function to a cache memory and at the same time, shortening the partial writing time. CONSTITUTION:A full write register 19 can hold the 32-bit data which is read out of a data array 12 of a cache memory 1. The register 19 is connected to the array 12 via gate/selector 18. At the same time, the gate/selector 18 is provided between a write buffer 15 which holds the write data or the internal buses 17a and 17b and the register 19. Then the gate/selector 18 is controlled in response to the byte control signal received from an MPU 2. Then the rewritten 32-bit data stored in the register 19 is stored in the array 12 based on the hit signal received from a tag comparator 14. The 32-bit data can also be transferred to an external memory. Thus the function and the working speed of the memory 1 can be improved.

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