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1. 发明专利

JP2002196886A TOUCH PANEL AND PICTURE INPUT TYPE DISPLAY DEVICE 失效
公开(公告)号：JP2002196886A
公开(公告)日：2002-07-12
申请号：JP2001082411
申请日：2001-03-22
申请人： HITACHI LTD , HITACHI CHIBA ELECTRONICS CO L , HITACHI DEVICE ENG
发明人： CHIBA SHINSAKU , SUZUKI SHIGEKI , KONO MASAO , KAKINUMA SATOSHI , KONDO YASUAKI
IPC分类号： G02F1/1333 , G06F3/03 , G06F3/033 , G06F3/041 , G06F3/045 , G09F9/00 , H01H11/00 , H01H13/70 , H01H13/712 , H01H36/00
摘要： PROBLEM TO BE SOLVED: To avoid the generation of a Newton ring by adhesively fixing upper and lower substrates in a seal area without generating slack. SOLUTION: An adhesive material forming an adhesive layer is constituted of one or more adhesive material application banks 11A, 11B of which printing widths for fixing the upper and lower substrates 1, 6 in an intra-plane non- parallel state in the seal area wound around the input area AR of a touch panel so that the height of a sticking gap between the upper and lower substrates 1, 6 is circulated on the outside of the input area AR are the same or different and the upper substrate 1 is adhesively fixed with the lower substrate 6 so as to be projected to the lower substrate 6.

2. 发明专利

JP2000292765A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2000292765A
公开(公告)日：2000-10-20
申请号：JP9751199
申请日：1999-04-05
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： CHIBA SHINSAKU , KONDO YASUAKI
IPC分类号： G09G3/18 , G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption by making a driving voltage supply means incorporate an output stage circuit which outputs a current only in the flowout direction from the driving voltage supply means and an output stage circuit which outputs a current only in the inflow direction. SOLUTION: An operational amplifier O'P2 in place of a conventional operational amplifier and an npn type transistor TR1 which has its base connected to the output terminal of the operational amplifier O'P2 and its emitter connected to the inverted input terminal of the operational amplifier O'P2 through a resistance are used. When the voltage of a load circuit (capacitor Cs) is lower than a driving voltage Vsh, the npn type transistor TR1 supplies a current Ish to the capacitor Cs to charge the capacitor Cs so that the voltage of the capacitor Cs approximates the Vsh. If the voltage of the capacitor Cs varies and the voltage of the capacitor Cs is higher than the driving voltage Vsh, the npn type transistor TR1 turns off. Consequently, no unnecessary current flows and the electric power is not wasted.

3. 发明专利

JPH075848A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH075848A
公开(公告)日：1995-01-10
申请号：JP16748093
申请日：1993-06-14
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU
IPC分类号： G02F1/133 , G09G3/36
摘要： PURPOSE:To simultaneously change output of a scanning driver and a data driver, to reduce power consumption and to improve quality of display by setting signal delay of a scanning driver side and a data driver side equally basing on the clock pulse as a reference. CONSTITUTION:An alternating signal M is inputted to a latch fetches circuit FF through an input buffer IB. This latch circuit FF the alternating signal M synchronizing with a clock pulse CL and transmits an alternating signal M' to a level shifter. And, both a scanning driver and a data driver are provided with an input buffer section, and fetch the same alternating signal M by the same clock pulse CL. Therefore, the alternating signal M' supplied to the level shifter in the scanning driver and the data driver is varied with same timing. Consequently, variation timing of driving voltage supplied to a scanning line electrode and a signal line electrode are made almost the same, and high voltage due to output time difference is not applied to liquid crystal.

4. 发明专利

JPS63197214A MEMORY DEVICE 失效
公开(公告)号：JPS63197214A
公开(公告)日：1988-08-16
申请号：JP2824287
申请日：1987-02-12
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU
IPC分类号： G06F3/06 , G11C11/14 , G11C19/08
摘要： PURPOSE:To ensure the complete compalitility between a memory and a floppy disk memory device by receiving the track shift signal from a floppy disk control device to count the up/down frequencies of the pulse designating the track shift frequency according to the track shift direction for detection of a designated track number. CONSTITUTION:A floppy disk control device FDC transmits a step signal STEP and a step direction signal DIR with a seeking instruction for track shift excluding the accesses on the same track. An interruption signal IRQ is produced via a peripheral interface adaptor PIA and synchronously with the front or back edge of the signal STEP. A microprocessor MPU identifies the level of the signal DIR in an interruption process and performs the addition or subtraction equivalent to a single step against the stored track number. The interruption processes are carried out for each signal STEP and therefore the addition or subtraction is performed in response to the number of signals STEP. Thus the track number to receive an access can be decided.

5. 发明专利

JPS63197086A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS63197086A
公开(公告)日：1988-08-15
申请号：JP2824187
申请日：1987-02-12
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To attain parallel action of plural bubble memory devices and to improve a data transfer rate by synchronizing plural bubble memory controllers, and actuating them. CONSTITUTION:Synchronization circuits SYNC1 and SYNC2 are provided in order to synchronize the bubble memory controllers BMC1-BMC4. Receiving an output signal from a level detection circuit LD which detects the entry/cut-off of a power source, the synchronization circuit SYNC2 generates a power on reset signal POR and a power down signal PD synchronizing with the clock signals of the bubble memory controllers BMC1-BMC4. Another synchronization circuit SYNC1 synchronizes the command fetching timing in the bubble memory controllers BMC1-BMC4. Thus, plural bubble memory controllers can be synchronized to actuate them, and the parallel action of plural bubble memory devices can be realized, so that the data transfer rate can be improved.

6. 发明专利

JPS61210597A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS61210597A
公开(公告)日：1986-09-18
申请号：JP5040885
申请日：1985-03-15
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To realize a voltage rise circuit obtainable a stable output voltage with a low cost by constituting an output voltage detecting circuit by a zener diode and a transistor and a resistance for dividing a potential. CONSTITUTION:By a voltage rise circuit comprising a frequency dividing flip flop (FF) circuit 11 having a clock signal input terminal 12 and an input terminal 13 of a power source voltage Vcc and a synchronizing FF circuit 14 and the like, an output of a diode pump circuit 15 rises and an output voltage VD of a predetermined value is obtained in an output terminal 21. When a potential dividing voltage of this output voltage VD is larger than a sum of a zener voltage of a zener diode 27 and a voltage between a base and an emitter of a transistor 28, the transistor 28 is turned on and outputs a reset input to a reset terminal of the frequency dividing FF circuit 11. Thereby, the output voltage VD becomes a constant voltage value. By enlarging the zener voltage, uneveness in the output voltage VD can be made small.

7. 发明专利

JPS61175991A CASSETTE-TYPE MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS61175991A
公开(公告)日：1986-08-07
申请号：JP1418885
申请日：1985-01-30
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU , FUTAMI TOSHIO
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To prevent the occurrence of malfunction due to static electricity by installing a grounding means between a magnetic bubble memory device main body and a magnetic bubble memory cassette case. CONSTITUTION:Where a cassette 10 is loaded on an adapter to attain the operable state, such an electircal conductive path is formed that the case 13 of the cassette 10 passes sequentially through a contact piece 8, a cassette attaching and detaching mechanism 6, a ground pattern 4 and a ground terminal 5. Therefore, when static electricity is impressed on the case 13, its charge flows quickly through said conductive path, and is discharged to the ground of the magnetic bubble memory device main body case. This means that the static electricity impressed on the case 13 does not flow a device 11 in the cassette 10, a sense amplifier circuit 12 and the signal ground systems of integrating circuits 2 and 3 of a printed circuit board 1, and accordingly the ground potentials of the circuits 2, 3 and 12 do not fluctuate. Thus the occurrence of an abnormal current is prevented, and the distruction of memory data stored in the device 11 is prevented.

8. 发明专利

JPS6083288A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS6083288A
公开(公告)日：1985-05-11
申请号：JP19070183
申请日：1983-10-14
申请人： HITACHI LTD
发明人： CHIBA SHINSAKU , TAKAHASHI KOUJI , YANO RIYUUJI
IPC分类号： G11C11/14
摘要： PURPOSE:To decrease a rush current in power-on operation and stabilize the operation, and turn off a power source when a magnetic bubble memory device is not in operation and reduce the power consumption by providing a switching element of a power on-off circuit with a time constant circuit which suppress the peak value of the rush current. CONSTITUTION:The CR time constant circuit consists of a capacitor C1 and a resistance R3. When a control signal voltage VCONT impressed to a terminal T3 exceeds the base-emitter voltage VBE of a transistor (TR) Q2, the TRQ2 turns on and an FETQ1 also turns on at the same time. In this case, the gate-source voltage VGS of the FETQ1 rises slower than a convertional circuit as shown by characteristics I because of the presence of said CR time constant circuit.

9. 发明专利

JPS6013386A MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS6013386A
公开(公告)日：1985-01-23
申请号：JP11827883
申请日：1983-07-01
申请人： HITACHI LTD
发明人： YOSHIDA KAZUTOSHI , CHIBA SHINSAKU , SUGIE MAMORU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To detect the number of packaged magnetic bubble memory devices without adding parts such as a switch by reading out map loop data of the magnetic bubble memory devices. CONSTITUTION:Index data DI for detecting addresses and defective loop data DN are stored in a map loop 2. If a magnetic bubble memory device 13 is not packaged, no signal is applied to the input of a sense amplifier 17, so that said state is the same as no output from the magnetic bubble memory device 13, i.e. the input data are ''0''. When the map loop data are all ''0''s at the reading-out of data from the map loop 2, it can be regarded that there is no magnetic bubble memory. Thus, the number of packaged magnetic bubble memory devices can be detected by reading out data in the map loop.

10. 发明专利

JPS59198589A Magnetic bubble memory controller 失效
标题翻译：磁性气泡记忆体控制器
公开(公告)号：JPS59198589A
公开(公告)日：1984-11-10
申请号：JP6994483
申请日：1983-04-22
申请人： Hitachi Ltd
发明人： YOSHIDA KAZUTOSHI , CHIBA SHINSAKU , TAKAYANAGI HIROSHI , SUGIE MAMORU
IPC分类号： G11C11/14 , G06F3/00 , G06F11/00 , G06F11/07 , G06F13/40
CPC分类号： G06F11/073 , G06F3/007 , G06F11/0751
摘要： PURPOSE: To quicken the reading time of a register of a data controller by controlling an output buffer of the data controller so as to be an open drain structure at simultaneous read.
CONSTITUTION: In case of simultaneous read of the data controller, a PREAD signal goes to an "H", resulting that an NMOS transistor (TR)12 is turned on/off depending the state of a DATA signal. That is, when the DATA signal is at the "H", the NMOS TR12 is turned on, and when an "L", the TR12 is turned off. On the other hand, in a PMOS TR13, an SREAD signal is at the "L" independently of the level of the PREAD signal and the TR13 is turned off at simultaneous reading. Thus, an OUT signal is in either OFF state depending on the content of the register at simultaneous read or ON stat of the NMOS TR12. In this state, the NMOS TR12 only is connected, and in case of the simultaneous read depending on the content of data, the NMOS TR12 is turned on or off and it is equivalent that no PMOSTR11 is provded.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过控制数据控制器的输出缓冲器来加快数据控制器寄存器的读取时间，以便同时读取时是一个开漏结构。构成：在同时读取数据控制器的情况下，PREAD信号变为“H”，导致NMOS晶体管（TR）12根据DATA信号的状态导通/截止。也就是说，当DATA信号为“H”时，NMOS TR12导通，当“12”为“L”时，TR12被关断。另一方面，在PMOS TR13中，SREAD信号独立于PREAD信号的电平为“L”，并且TR13在同时读取时被关断。因此，根据NMOS TR12的同时读或ON状态下的寄存器的内容，OUT信号处于OFF状态。在这种状态下，只有NMOS TR12被连接，并且在根据数据的内容进行同时读取的情况下，NMOS TR12导通或截止，并且等同于没有提供PMOSTR11。

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