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51. 发明专利

JPS6367194A IC CARD 失效
公开(公告)号：JPS6367194A
公开(公告)日：1988-03-25
申请号：JP21155686
申请日：1986-09-10
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE
IPC分类号： G06K19/08 , B42D15/02 , B42D15/10 , G06K19/00

52. 发明专利

JPS628397A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS628397A
公开(公告)日：1987-01-16
申请号：JP14471985
申请日：1985-07-03
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , SAWASE TERUMI
IPC分类号： G11C17/00 , G11C16/02 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To make variable writing and deleting time by constituting a writing and deleting time control circuit by a timer to synchronize with an external clock and a register to set the period. CONSTITUTION:A timer counter 8 can set the time by a data line 92, synchronize with the writing and deleting starting signal, start to count the time and generate a control signal 95 of the setting time width only. Namely, for a zero detecting circuit 83, the data set to the register beforehand from the data line are loaded to a down-counter 82 by a starting signal 93, and simultaneously, down-counting is executed by a clock input 94. The zero detecting circuit 83 decides the contents of the counter 82 and in case of zero, outputs a control signal 95. Since the writing or deleting time can be optionally set, when the holding time is short or long, the time is adjusted and the high reliability and the suitable processing time can be realized.

53. 发明专利

JPS5934009B2 JPS5934009B2 - 失效
公开(公告)号：JPS5934009B2
公开(公告)日：1984-08-20
申请号：JP12510278
申请日：1978-10-13
申请人： Hitachi Ltd
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , TAKAI ATSUSHI , KIDA JUZO , PPONDA AKIRA
IPC分类号： H03J7/02 , H03J5/00 , H03J5/02 , H04B1/26

54. 发明专利

JPS59132496A Memory 失效
标题翻译：记忆
公开(公告)号：JPS59132496A
公开(公告)日：1984-07-30
申请号：JP18301583
申请日：1983-10-03
申请人： Hitachi Ltd
发明人： TAKAI ATSUSHI , KIDA YUUZOU , HAGIWARA YOSHIMUNE , SAWASE TERUMI , HAGIWARA TAKAAKI
IPC分类号： G11C16/02 , G11C17/00
CPC分类号： G11C17/00
摘要： PURPOSE:To prevent a voltage mode changing the storage content of a memory cell not erased from being given to a memory cell at partial erase of a memory by controlling a sequence of a voltage given to each terminal of nonselecting memory cell. CONSTITUTION:In figure, 90 is the entire board of a memory IC and 94 is a memory cell itself. A terminal 91 is connected to the board and coupled electrically to the board of transistors (TRs) of the entire substrate. A board voltage Vp is given by turning on a switch 21 to a terminal 22 of which the voltage Vp is given. A signal line 93 is connected to sources of longitudinal TRs, a terminal 95 is connected to a switch 45 and a voltage Vwd is given to a terminal 6. A sensor 53 is connected to the other terminal 96 of the signal line 93. A signal line 31 is connected to gates of a lateral TRs and one terminal 98 is connected to a switch 14. The voltage Vp is given to a terminal 15 at non-erasing state and 0V is given at erasing state.
摘要翻译：目的：为了防止电压模式通过控制给予非选择性存储单元的每个端子的电压的顺序来改变不擦除的存储器单元的存储内容，从而被赋予存储器部分擦除存储器。规定：在图中，90是存储器IC的整个板，94是存储单元本身。端子91连接到电路板，并且电连接到整个衬底的晶体管板（TR）。通过将开关21接通到给定电压Vp的端子22来给出板电压Vp。信号线93连接到纵向TR的源极，端子95连接到开关45，并且电压Vwd被提供给端子6.传感器53连接到信号线93的另一个端子96。线31连接到横向TR的栅极，一个端子98连接到开关14.电压Vp在非擦除状态下被提供给端子15，并且在擦除状态下给出0V。

55. 发明专利

JPS5552591A DRIVING METHOD FOR MEMORY 失效
公开(公告)号：JPS5552591A
公开(公告)日：1980-04-17
申请号：JP12362578
申请日：1978-10-09
申请人： HITACHI LTD
发明人： TAKAI ATSUSHI , KIDA YUUZOU , HAGIWARA YOSHIMUNE , SAWASE TERUMI , HAGIWARA TAKAKATSU
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26
摘要： PURPOSE:To prevent ROM(EAROM), which is unselected and electrically rewritable in partial erasing operation from being momently in a write or erasing state, by partially erasing a memory after increasing the source voltage of a memory cell up to a fixed value. CONSTITUTION:Since one terminal of exclusive-OR gate 2 is unselected, applying a high-level erasing instruction to terminal 1 at the time of a low level closes switch 5 to apply non-erasing voltage Vwd from terminal 6 to the source and a difference between the source and substrate of EAROM cell 50 becomes equal to Vwd. Consequently, the output of D latch 8 is held at a high level and switch 14 is closed to develop a potential difference of Vp between the substrate and gate of cell 50 by erasing state voltage Vp from terminal 15. At the same time, the output of sensor 55 is also held at a high level, and switch 21 is closed through AND gate 17 to make the gate level of cell 50 equal to its substrate level by voltage Vp from terminal 22, so that the unselected ROM cell can be prevented from being momently in a write or erasing state during partial erasing operation.

56. 发明专利

JPS5336261A NOISE REMOVER 失效
公开(公告)号：JPS5336261A
公开(公告)日：1978-04-04
申请号：JP10996476
申请日：1976-09-16
申请人： HITACHI LTD
发明人： TOKINAGA DAIZOU , SAWASE TERUMI
IPC分类号： H04B1/10 , G01D5/12 , G08C25/00 , H04B15/00
摘要： PURPOSE:Easy removing of power supply frequency noises is made possible by generating the alternating current of the same frequency as that of noise component, inverting the phase therof and adding it to the signal from the test body.

57. 发明专利

JPS5265046A NUTRITIOUS SOLUTION CULTIVATING DEVICE 失效
公开(公告)号：JPS5265046A
公开(公告)日：1977-05-30
申请号：JP14021475
申请日：1975-11-25
申请人： HITACHI LTD
发明人： KANEKO TADAO , MORITA OSAMU , TAKATSUJI MASAKI , SAWASE TERUMI
IPC分类号： A01G31/00 , A01G31/04

58. 发明专利

JPH08153082A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SIGNAL PROCESSING METHOD 失效
公开(公告)号：JPH08153082A
公开(公告)日：1996-06-11
申请号：JP8957895
申请日：1995-04-14
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NOGUCHI YOSHIKI , NAKAMURA HIDEO
IPC分类号： G06F15/78
摘要： PURPOSE: To arbitrarily constitute the logical function of a logic circuit in conformity with information written from the outside by constituting the logic circuit of an electrically writable non-volatile semiconductor memory element inside a single chip microcomputer. CONSTITUTION: The single chip microcomputer is constituted of a processor 5 consisting of a CPU 2, a RAM 3 and a ROM 4, a programmable logic array(PLA) 6 as the logic circuit device of variable logical structure, and an input/ output port (I/O) 7 on the same semiconductor substrate 1, and each block is connected by a common bus 8. Besides, the PLA 6 is connected directly to the I/O 7 and the CPU 2 by signal lines 9, 10. The ROM 4 is used for storing the software (program) of the single chip microcomputer. Besides, the PLA 6 acts as a logical device for realizing the hardware of the single chip microcomputer, and this PLA 6 contains the electrically writable non-volatile memory element.

59. 发明专利

JPH0668684A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0668684A
公开(公告)日：1994-03-11
申请号：JP3927091
申请日：1991-02-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ITO HISANORI , MASUMURA SHIGEKI , NAKAMURA HIDEO , HAYASHI MAKOTO , SAWASE TERUMI , MATSUBARA KIYOSHI , AKAO YASUSHI
IPC分类号： G06F7/00 , G06F15/78 , G11C11/417 , G11C16/06 , G11C17/00
摘要： PURPOSE:To reduce current consumption for reading operation, even if access time of a memory cell of which access time is slow is not considered and variation of access time actually varied is comparatively large depending on selected memory cells. CONSTITUTION:In operation for reading data of memory cells M1-M8, a state in which data is actually read out from memory cells M9-M12 as a discriminating bit is detected by a detecting circuit 11, current stopping circuits 13 and 14 are operated synchronizing with it, and sense amplifiers 6a-6c is made non- activation. Also, all word lines W1-W4 are forced to set to a low level, and all memory cells are controlled in non-selection state. Thereby, a stationary current flowing to a memory is stopped. Therefore, a stationary current flowing to a memory is stopped with fast timing when access time is fast, and stopped with slow timing when access time is slow, then current consumption is reduced in actual operation.

60. 发明专利

JPH04169915A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04169915A
公开(公告)日：1992-06-17
申请号：JP29532090
申请日：1990-11-02
申请人： HITACHI LTD
发明人： MORIKAWA MASATOSHI , YOSHIDA ISAO , SAWASE TERUMI , SAKAMOTO MITSUZO , OKABE TAKEAKI
IPC分类号： G06F1/00 , G01Q70/00 , G05F1/56 , H01L21/822 , H01L27/04 , H03K17/08 , H03K17/082 , H03M1/08
摘要： PURPOSE:To obtain a semiconductor integrated circuit having a high chip temperature control function by processing the electric signal generated from a sensor in accordance with the program stored in a memory by a CPU and setting the driving capability of an output semiconductor element in accordance with the processing result. CONSTITUTION:A microprocessor unit 2 consisting of a memory 20 and a CPU 22 is provided in a semiconductor chip 1 also. The program to execute the chip temperature control is stored in a memory 20 of a microprocessor unit 2, and an electric signal 7 generated from a sensor 5 is processed by the CPU 22 in accordance with the program stored in the memory 20. Consequently, the driving capability of an output semiconductor element 3 is set to the optimum state correspondingly to the momently changing chip temperature. Thus, the semiconductor integrated circuit having the high chip temperature control function is obtained.

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