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51. 发明专利

JPS60578A CHARACTER RECOGNIZING SYSTEM 失效
公开(公告)号：JPS60578A
公开(公告)日：1985-01-05
申请号：JP10895483
申请日：1983-06-17
申请人： SANKYO SEIKI SEISAKUSHO KK , FUJITSU LTD
发明人： OKUHARA TORAYUKI , HAMANO YUTAKA , YAMAMOTO HIROYUKI
IPC分类号： G06K9/00
摘要： PURPOSE:To improve the rate of character recognition by lowering the noise slice level stepwise to perform the character recognition when the character recognition is impossible. CONSTITUTION:Read data is stored in a read data storing device 1 and a peak detecting memory 2 takes out data of peak value above a fixed slice level from the content of the device 1 and stores. A character code preparing device 3 prepares a character code by using stored contents of the device 2, and a character recognizing device 4 correlates the character code with a specific fixed code and reads and recognizes characters. When the device 4 can not recognize the read characters, the device 2 lowers the slice level stepwise and takes out data of peak value above the slice level from the content of the device 1 and stores. The device 3 and device 4 perform preparation of character code and recognition of characters according to the data.

52. 发明专利

JPS60575A MAGNETIC INK CHARACTER READING DEVICE 失效
公开(公告)号：JPS60575A
公开(公告)日：1985-01-05
申请号：JP10845883
申请日：1983-06-16
申请人： SANKYO SEIKI SEISAKUSHO KK , FUJITSU LTD
发明人： ORII TSUTOMU , HAMANO YUTAKA , YAMAMOTO HIROYUKI
IPC分类号： G06K9/00
摘要： PURPOSE:To enable correct character recognition even when there are blots, voids etc. of magnetic ink characters by reading magnetic ink characters magnetically attracted by AC, rectifying and taking out only low-pass components through an LPF. CONSTITUTION:An AC signal is applied to a magnetic head 1 from an oscillator 4, and magnetic ink characters of running medium 3 are magnetized basing on the AC signal. Magnetized characters are read by a reading head 2. The reading signal is amplified by an amplifier 5, rectified by a rectifier 6 and only its low- pass components are taken out by an LPF 7. Accordingly, only integration signal corresponding to magnetic ink characters is taken out. This signal waveform becomes a waveform proper to each character, and therefore, characters can be recognized by comparing the signal waveform with predetermined specific patterns.

53. 发明专利

JPS5930299B2 JPS5930299B2 - 失效
公开(公告)号：JPS5930299B2
公开(公告)日：1984-07-26
申请号：JP3299179
申请日：1979-03-20
申请人： Fujitsu Ltd
发明人： IMAI TADAAKI , YAMAMOTO HIROYUKI , KOBAYASHI MASAAKI , AZUMA MASAYUKI
IPC分类号： H04L29/02 , G06F13/00 , H04L13/00

54. 发明专利

JPS593687A Cash control system 失效
标题翻译：现场控制系统
公开(公告)号：JPS593687A
公开(公告)日：1984-01-10
申请号：JP11358782
申请日：1982-06-30
申请人： Fujitsu Ltd
发明人： YAMAMOTO HIROYUKI
IPC分类号： G07D13/00 , G06Q40/00 , G06Q40/02 , G07D9/00 , G07F19/00
CPC分类号： G06Q40/02
摘要： PURPOSE:To improve the operating rate of a device by storing paper currency in a safe immediately when the amount of money of a paying-in slip is equal to that counted by a paying-in machine, and returning paper currency automatically from a dispenser by the same amount of money in case of a failure of transaction. CONSTITUTION:The amount of money counted by the paper currency paying-in machine AD6 is compared 10 by a comparator with the amount of money inputted on a keyboard 5 on the basis of a paying-in slip through buffers 9 and 8. When both are equal to each other, the paper currency is stored immediately in the safe from an intermediate pool which is not shown in a figure and that is reported to a host computer 13. The host computer 13 returns an OK signal when the transaction is concluded, but returns a transaction failure signal when not, for example, when an account number is not coincident to send an paying- back indication 18 of the amount of money in an AD buffer 6 through an AND circuit 16, paying back the money from the dispenser AC7 automatically. Consequently, the time when paper currency stays in the intermediate pool is shortened to improve the operating rate of the device that two tellers are in charge of.
摘要翻译：目的：通过将付款单的金额等于由付款机计算的金额，并立即将纸币从分配器自动返回，通过将纸币存入保险箱，立即将纸币存入保险箱，以提高设备的运行率在交易失败的情况下的相同金额。规定：由纸币付款机器AD6计算的金额由比较器10与基于通过缓冲器9和8的支付单据输入的键盘5的金额进行比较。当两者都是彼此相等，纸币从图中未示出并被报告给主计算机13的中间池立即存储在保险箱中。主计算机13在交易结束时返回OK信号，但是当不是例如当帐号不符合通过AND电路16发送AD缓冲器6中的金额的付款指示18时返回交易失败信号，从分配器AC7返还货币自动。因此，纸币滞留在中间池的时间被缩短，以提高两个柜员负责的装置的运行速度。

55. 发明专利

JPS589458B2 失效
公开(公告)号：JPS589458B2
公开(公告)日：1983-02-21
申请号：JP7827278
申请日：1978-06-28
申请人： FUJITSU LTD
发明人： TAKABA KINZO , TSUBOI HIDEO , YAMAMOTO HIROYUKI , NAGANO YOSHIHIRO
IPC分类号： G06F15/16 , G06F1/04 , G06F1/14 , G06F15/177

56. 发明专利

JPS55127749A TRANSMISSION CONTROL CIRCUIT 失效
公开(公告)号：JPS55127749A
公开(公告)日：1980-10-02
申请号：JP3527879
申请日：1979-03-26
申请人： FUJITSU LTD
发明人： IMAI TADAAKI , YAMAMOTO HIROYUKI , KOBAYASHI MASAAKI , AZUMA MASAYUKI
IPC分类号： H04L5/16 , G06F13/00 , H04L25/45 , H04L29/02 , H04L29/06
摘要： PURPOSE:To make half-duplex communication possible by providing a circuit which performs inter-frame time fill IFTF of a flag pattern under the idle state and performs IFTF of the pattern of all marks in case that transmission abandonment is dispalyed. CONSTITUTION:After stored in data register 11, write data WD from LA (line adapter) bus is transferred to P/S serial.parallel register 12 under the parallel state. Register adds flag F, etc., to input data and transmits it under the serial state. If the FF in control circuit is ''0'', flag generator 15' is operated, and the flag is supplied to register 12 to obtain a pattern with flag F inserted to inter-frame IFT. If the FF is ''1'' under the idle state, mark generator 15 is selected, and signals 1, 1...1 are transmitted from mark generator 15 to line 14 through gate 13. Control circuit 10 is controlled by register address RA.

57. 发明专利

JPS55124841A DATA RECEPTION CONTROL UNIT 失效
公开(公告)号：JPS55124841A
公开(公告)日：1980-09-26
申请号：JP3299179
申请日：1979-03-20
申请人： FUJITSU LTD
发明人： IMAI TADAAKI , YAMAMOTO HIROYUKI , KOBAYASHI MASAAKI , AZUMA MASAYUKI
IPC分类号： H04L29/02 , G06F13/00 , H04L13/00
摘要： PURPOSE:To make easy the control including CRC register and to avoid unnecessary interruption, to bit serial for the data transfer between the reception registers, by providing four reception registers of 1 byte capacity possible for transmission control in HDLC (High level Data Link Control). CONSTITUTION:The data in HDLC step is written in the reception register 31 via the 0 delete circuit 37, and write-in to the reception register 32 of the reception data is made at the register control 39 when flag F is detected at the flag detection circuit, and 8-bit data is transferred to the registers 33-36 in bit serial after that. The counter 42 performs count every 1 byte and the count value of 4 is reached, then the reception of minimum frame constitution is confirmed to inform it to program and request read-in, and if no minimum frame constitution is given, no read- in request is made. In parallel with the shift operation, error check by CRC register 40 is made and the result is informed to the program.

58. 发明专利

JPS5587273A CASH REGISTER 失效
公开(公告)号：JPS5587273A
公开(公告)日：1980-07-01
申请号：JP15914378
申请日：1978-12-26
申请人： FUJITSU LTD
发明人： HAMANO YUTAKA , MATSUMOTO TSUTOMU , TANAKA TOSHIYUKI , YAMAMOTO HIROYUKI , KUROKI AKIRA , SUZUKI AKIRA , UETAKE MITSUO
摘要： PURPOSE:To prevent an error from occurring by verifying the total numbers of sheets by kinds of money and kinds of bonds by comparing the total numbers of sheets by kinds of money and kinds of bonds calculated from the numbers of sheets by kinds of money and kinds of bonds with the newly-recounted numbers of sheets, and then by providing error display when the both disagree each other. CONSTITUTION:Input data are stored in register group 4. Among register group 4, the numbers of sheets of money by kinds of money are stored in registers 41-44, and the amount of money is in register 45; and the numbers of sheets by kinds of bonds are registered in registers 46 and 48, the amounts of bonds are stored in registers 47 and 49, and payment and receipt amounts on a slip are stored in register 50. To the itemized numbers of sheet and amounts stored, the number of sheets and amount inputted from input registers 53 and 54 are added by using adder group 7 and results are stored in register group 4 again. Data stored are used to calculate the total number of sheets, that of bonds, and the total amounts by kinds of operators 81-83, and results are compared with values of input registers 51 and 52, and register 50; when they are disagree mutually, error display is provided by display unit 88.

59. 发明专利

JPS5587269A CASH REGISTER 失效
公开(公告)号：JPS5587269A
公开(公告)日：1980-07-01
申请号：JP15912878
申请日：1978-12-26
申请人： FUJITSU LTD
发明人： OKUYAMA RIYOUICHI , NAGANO YOSHIHIRO , TSUBOI HIDEO , YAMAMOTO HIROYUKI
摘要： PURPOSE:To reduce the possibility of the occurrence of an error by deciding on whether the result of subtraction of a subtrahend from a minuend of every process is positive or negative, and then by displaying it on part of a data display part. CONSTITUTION:Data having passed through main task 32 are stored in item buffer memory 36 and then transferred to data display part 13 by way of control part 35, main task part 32, and control parts 37 and 42 to display respective items in corresponding areas. Every time data is inputted, counter arithmetic part 33 updates corresponding data by adding or subtracting. With an end key depressed, count arithmetic program control part 33-2 calculates a difference amount between an input amount stored in counter memory 34 and itemized data. When the difference amount is zero, the contents of memory 34 are transferred to a center by processing part 43 via transmission control part 38.

60. 发明专利

JPS554676A TIMER CONTROL SYSTEM FOR DATA PROCESS SYSTEM 失效
公开(公告)号：JPS554676A
公开(公告)日：1980-01-14
申请号：JP7827278
申请日：1978-06-28
申请人： FUJITSU LTD
发明人： TAKABA KINZOU , TSUBOI HIDEO , YAMAMOTO HIROYUKI , NAGANO YOSHIHIRO
IPC分类号： G06F15/16 , G06F1/04 , G06F1/14 , G06F15/177
摘要： PURPOSE:To save the memory capacity necessary for the timer subroutine with no waste through sharing of the timer subroutine by plural microprocessors. CONSTITUTION:Microprocessors A and B possess control memories CM1 and CM2 as the prescribed process means plus order execution units PU1 and PU2 as the process units, and the transfer is given to the next process step in case the fixed time elapses from a fixed time. In such data process system, jump address table 9 to store the order of the timer subroutine plus input/output boats IP1 and IP5 are provided to processor A, and input/output boats IP2, IP4 and IP5, timer table memory 12 plus clock generator 13 are provided to processor B respectively. Thus, the timer subroutine can be shared, decreasing the memory capacity necessary for the timer subroutine.

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