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51. 发明专利

JPH0629956A ERROR CORRECTION CODE INSERT PROCESSING SYSTEM IN SDH SIGNAL AND OPTICAL TRANSMITTER 失效
公开(公告)号：JPH0629956A
公开(公告)日：1994-02-04
申请号：JP23106792
申请日：1992-08-31
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H04B10/556 , H04B10/2507 , H04J3/00 , H04L1/00 , H04B10/00
摘要： PURPOSE:To provide an error correction function to an SDH signal in the concatenation mode by applying error correction arithmetic operation to data of each string of pay load so as to generate an error correction code thereby inserting the code to a stuff field of a succeeding string. CONSTITUTION:A generating means 3 applies error correction arithmetic operation to data of each string of pay load to generate an error correction code and an insert means 4 inserts the error correction code to, e.g. a stuff field of a succeeding string. A section overhead SOH insert means 5 inserts control information to generate an SOH frame. The generating means 3 applies parallel error correction arithmetic operation to data of plural strings of pay load to generate an error correction code, then the insert means 4 inserts the plural error correction codes to a relevant stuff field in parallel. Thus, the error correction code is inserted to an SDH signal in the concatenation mode in compliance with the Modified G.709.

52. 发明专利

JPH04240936A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPH04240936A
公开(公告)日：1992-08-28
申请号：JP745891
申请日：1991-01-25
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H04L7/033
摘要： PURPOSE:To simplify the phase matching by using an output of a PLL circuit as a recovery clock and obtaining an output data with matched phase from a reception data string with the clock. CONSTITUTION:A sender side clock insert means 1 inserts a clock to part of a sent data string and sends the data string with the clock inserted thereto to a receiver side through a single transmission line 2. The receiver side uses a clock extracted from a reception data string as a reference input to control an output phase of a voltage controlled oscillator VCO of a PLL circuit 3 and an output when the phase is coincident with a phase of the reference input is used as the recovered clock. Then an output data in matching with the phase of the clock is obtained from the reception data string by using the recovered clock.

53. 发明专利

JPH0336337B2 失效
公开(公告)号：JPH0336337B2
公开(公告)日：1991-05-31
申请号：JP12882183
申请日：1983-07-15
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H03K19/018 , H03K17/14 , H03K17/60 , H03K17/66

54. 发明专利

JPH02230822A VITERBI DECODER 失效
公开(公告)号：JPH02230822A
公开(公告)日：1990-09-13
申请号：JP5121289
申请日：1989-03-03
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H03M13/23
摘要： PURPOSE:To reduce the power consumption by turning off the power supply to a memory element unnecessary in use whose output path is identical to that of other element after certain and succeeding stages on the way of a path memory when a code error rate of an input signal is changed into an excellent state. CONSTITUTION:When the code error rate of an error correction coding signal is varied from the worst state into an excellent state and the number of surviving paths outputted from a Viterbi arithmetic section 1 is decreased, the output pulse from elements after certain and succeeding stages on the way of a path memory 2 storing surviving paths are identical, and circuits of elements after the stage are redundant circuits. Then an error rate detection section 4 detects a rate better than a prescribed error rate and generates a detection signal (d) and sends the signal to the path memory 2. Then the path memory 2 turns off the power supply to memory elements unnecessary in use after certain and succeeding stages being redundancy circuits by the detection signal (d) of the error rate detection section 4. Thus, the power consumption is reduced.

55. 发明专利

JPH01149521A SYSTEM FOR GENERATING CLEAR PULSE 失效
公开(公告)号：JPH01149521A
公开(公告)日：1989-06-12
申请号：JP30792087
申请日：1987-12-04
申请人： FUJITSU LTD
发明人： SUDA ATSUSHI , SUZUKI TERUHIKO , ITO ATSUSHI
IPC分类号： H03K21/38 , H03K23/00 , H03K23/50
摘要： PURPOSE:To surely generate a clear pulse by outputting the clear pulse from the time of the change of a first signal to the time of the change of a third signal. CONSTITUTION:When an input signal a2 is changed to a logic '1' at the time of a t21, a flip-flop 11 is set at the time of a t22 when a clock signal clk1 falls first after a certain time, and a signal b2 outputted from a terminal Q is set to the logic '1'. When the output signal b2 is changed to the logic '1', a flip- flop 12 sets a signal c2 outputted from the terminal Q to the logic '1'. Since a flip-flop 13 sets an output signal d2 outputted from a terminal Qn to a logic '0' when the output signal c2 is changed to a logic '1', a clear signal e2 is reset to the logic '1'.

56. 发明专利

JPS6051351A BIPHASE CODE IDENTIFYING CIRCUIT 失效
公开(公告)号：JPS6051351A
公开(公告)日：1985-03-22
申请号：JP15951683
申请日：1983-08-31
申请人： FUJITSU LTD
发明人： SUZUKI TERUHIKO
IPC分类号： H03M5/12 , H04L25/40 , H04L25/49
摘要： PURPOSE:To prevent a margin of code identification from being reduced even if a duty ratio is changed 50% from normal state, by allowing the rise of an identifying clock to come automatically to the center of a received waveform where the mark rate is changed. CONSTITUTION:If the duty ratio of the signal of a CMI code is deviated from 50%, a code string where a DC potential is changed is inputted to an input 1 of an operational amplifier 1. Consequently, an output DC voltage EC of the operation amplifier 1 is changed. This changed DC voltage changes the capacity of a varactor diode 3 to change the turning frequency of a tuning circuit 31. This change of the clock frequency is set in accordance with the change of the duty ratio of the CMI code so that the rise of the clock comes to the center of the received code waveform where the duty ratio is changed. Thus, the margin of code identification is increased to minimize the code error in a identifying circuit.

57. 发明专利

JPS5932936B2 JPS5932936B2 - 失效
公开(公告)号：JPS5932936B2
公开(公告)日：1984-08-11
申请号：JP21071181
申请日：1981-12-30
申请人： Fujitsu Ltd
发明人： TOMIMORI KYOSHI , ARAI MASANORI , NISHIZAKI KOJI , SUZUKI TERUHIKO
IPC分类号： H04B3/46 , H04B17/00 , H04L1/20 , H04L25/02
CPC分类号： H04L1/20

58. 发明专利

JPS59100642A ALARMING CIRCUIT OF SIGNAL INTERRUPTION 失效
公开(公告)号：JPS59100642A
公开(公告)日：1984-06-09
申请号：JP21011682
申请日：1982-11-30
申请人： FUJITSU LTD
发明人： ARAI MASANORI , NISHIZAKI KOUJI , SUZUKI TERUHIKO
IPC分类号： H03K5/19 , H04B1/74 , H04B17/00 , H04B17/18 , H04B17/29 , H04L1/22 , H04L25/02
摘要： PURPOSE:To simplify the maintenance when a spare transmission line is used by constituting the circuit of a signal interruption detecting circuit reset when a signal is given and set when the signal is interrupted, an FF set by this output and an AND gate. CONSTITUTION:An output of a signal interruption detecting circuit SIG goes to an L level when a signal exists at an input terminal (a) and goes to an H level when no signal exists. Since a signal is inputted to the SIG at an existing N side, the FF is reset and no signal appears at an output terminal (b) of the when no signal is applied to the terminal (a), the output of the SIG goes to the H level, the FF is set, both the inputs of the AND circuit goes to the H level, and a signal interruption alarm output is generated at the terminal (b). In depressing a switch SW, the FF is reset and the signal interruption alarm is stopped. When the set is used as a spare set S side, although the output of the SIG goes to the H level, the FF is reset, the output of the AND circuit goes to the L level and the signal interruption alarm output remains stopped.

59. 发明专利

JPS5961217A Circuit for detecting interruption of clock 失效
标题翻译：用于检测时钟中断的电路
公开(公告)号：JPS5961217A
公开(公告)日：1984-04-07
申请号：JP17235382
申请日：1982-09-29
申请人： Fujitsu Ltd
发明人： SUZUKI TERUHIKO , ARAI MASANORI , MIYAKI YUUJI
IPC分类号： H03K5/19
CPC分类号： H03K5/19
摘要： PURPOSE:To detect the short interruption of clocks precisely by dividing an input and an oscillation output at their frequency respectively and then comparing their phases at the detection of the interruption of input clocks in a phase synchronous oscillation circuit. CONSTITUTION:Outputs (a), (b) from frequency dividers 1, 4 for input and output clocks respectively are equally divided by N in 1/N dividers 7, 8, which generate outputs (d), (e). A phase comparator 2 compares the outputs (d), (e) at their phases and generates an output signal corresponding to the phase difference between both inputs (d), (e). After removing a noise component through a low pass filter 5, said output signal is fed back to a voltage control oscillator 3 as a control signal (f) to control the oscillation frequency and to make the oscillator 3 act as a phase synchronous oscillator circuit. Even if clock interruption of the input (a) is the same, the output (f) of the low pass filter 5 is sharply changed and the detection of clock interruption can be precisely detected.
摘要翻译：目的：通过分别输入和振荡输出分别精确检测时钟的短暂中断，然后在相位同步振荡电路中检测输入时钟中断时的相位进行比较。构成：输入和输出时钟的分频器1,4的输出（a），（b）分别由产生输出（d），（e）的1 / N分频器7,8中的N等分。相位比较器2比较其相位处的输出（d），（e），并产生对应于两个输入（d），（e）之间的相位差的输出信号。在通过低通滤波器5去除噪声分量之后，将所述输出信号作为控制信号（f）反馈到压控振荡器3，以控制振荡频率，并使振荡器3充当相位同步振荡电路。即使输入（a）的时钟中断相同，低通滤波器5的输出（f）急剧变化，也可以精确地检测出时钟中断的检测。

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