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51. 发明专利

JPH0322717A DATA COMMUNICATION EQUIPMENT FOR MOBILE RADIO 失效
公开(公告)号：JPH0322717A
公开(公告)日：1991-01-31
申请号：JP15707289
申请日：1989-06-20
申请人： TOSHIBA CORP , FUJITSU LTD , MITSUBISHI ELECTRIC CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： OBA RYOHEI , TSUKUI YASUHIRO , HANAWA TETSUYA , TAKEGAKI HIROSHI , INOUE KOICHI
IPC分类号： H04B7/26 , H04B1/38 , H04W4/00 , H04W68/00 , H04W92/08
摘要： PURPOSE:To make an incoming indication even when a radio modem equipment and a data terminal device are disconnected by making the incoming indication by an informing means provided in a radio modem equipment. CONSTITUTION:A voltage detector 14 detects whether or not the output voltage of a battery 22 is supplied to a microcomputer 20 in a data terminal equipment 2 by turning on the power switch 21 of the data terminal device 2 through a cable 4. If an incoming signal arrives from an opposite station while the detector detects the data terminal equipment 2 not being in operation, a buzzer 15 in a radio modem device 1 makes an incoming indication. Consequently, the incoming indication can be made even when the radio modem equipment 1 and data terminal equipment 2 are disconnected.

52. 发明专利

JPH02301852A DATA TRANSFERRING SYSTEM 失效
公开(公告)号：JPH02301852A
公开(公告)日：1990-12-13
申请号：JP12345489
申请日：1989-05-17
申请人： FUJITSU LTD
发明人： INOUE KOICHI
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177
摘要： PURPOSE:To reduce the labor and time required for data transfer by storing plural identification codes in each processor which receives packets and performing data fetching when selected identifying information coincides with recipient identifying information after selecting the identifying information in accordance with the selecting information in a packet. CONSTITUTION:Plural identification codes are stored in an identification code storing means 121 and an identification code designating means 131 designates and reads out one of the plural codes on the basis of selecting information supplied from a receiving means 111. The read-out identification code is inputted to a comparator means 141 together with a recipient identifying code outputted from the receiving means 111 and whether or not the codes coincide with each other is discriminated by comparison. When the codes are coincident, the data contained in a packet are fetched by a data fetching means 151 to a processor itself. Therefore, the labor and time required for data transfer are reduced.

53. 发明专利

JPH0277959A BUS ARBITRATING SYSTEM 失效
公开(公告)号：JPH0277959A
公开(公告)日：1990-03-19
申请号：JP23071988
申请日：1988-09-14
申请人： FUJITSU LTD
发明人： INOUE KOICHI , IKESAKA MORIO
IPC分类号： G06F15/16 , G06F13/362 , G06F15/177
摘要： PURPOSE:To avoid the processing stay of a bus arbitrating system as a whole by adding a means which designates each processor to a bus arbiter of a host processor, etc., together with a means which arbitrates the bus using requests to a common bus. CONSTITUTION:When a processor (#0) 2 has no bus acquiring request, a bus acquiring signal BAQ is set at 0 and an AND circuit 14 sends a clock to an ID counter 11 and then transmits ID = 1. As a result, a comparator 22 transmits the coincidence output and catches a bus allocation signal BAB via an AND circuit 23 to set the signal BAQ at 1. When the signals BAQ is received by a host processor 1, an FF 13 is released from a clear state. Then the FF 13 outputs 1 in case a flag signal showing the transfer of data larger than a prescribed quantity is kept at 1. Thus the circuit 14 is suppressed and the count-up action of the counter 11 is stopped. Then the bus using right is fixedly given to a processor (#1) 2.

54. 发明专利

JPS63262766A DECENTRALIZED PICTURE DATA DISPLAY CONTROL SYSTEM 失效
公开(公告)号：JPS63262766A
公开(公告)日：1988-10-31
申请号：JP9650087
申请日：1987-04-20
申请人： FUJITSU LTD
发明人： ISHIHATA HIROAKI , KAKIMOTO MASANORI , INOUE KOICHI
IPC分类号： G06F15/16 , G06F9/52 , G06F15/163 , G06F15/167 , G06F15/177 , G06F15/80 , G06T11/00
摘要： PURPOSE:To dynamically set an assigned area and to divide and control a picture in a real time by providing a means for storing the assigned area information of a cell and a means for determining the assigned area based on the contents of this storage in the respective cells. CONSTITUTION:Based on an instruction from a host computer 13, the assigned area information of respective processor elements (cell) 10 is set to an assigned area information storing circuit 24 by a processor 12. Based on the contents of this setting, the assigned area of its own cell 10 is determined by an assigned area decision circuit 25 and based on the output signal of the circuit 25, the address of a picture memory 11 for storing picture data relating to this assigned area is generated in a picture memory address generating circuit 23. The competition of an access to the memory 11 of the processor 11 for processing the picture data relating to this assigned area and an access to the memory 11 by the address from the circuit 23 for reading the displayed picture data is adjusted by an access competition adjusting circuit 21.

55. 发明专利

JPS61288255A INTER-PROCESSOR COMMUNICATION CONTROL SYSTEM 失效
公开(公告)号：JPS61288255A
公开(公告)日：1986-12-18
申请号：JP13100785
申请日：1985-06-17
申请人： FUJITSU LTD
发明人： IKESAKA MORIO , SATO KEIJI , INOUE KOICHI
IPC分类号： G06F15/16 , G06F13/00 , G06F13/38 , G06F15/163 , G06F15/177
摘要： PURPOSE:To improve the operating efficiency of a processor having high processing speed in a reception side by transmitting plural packets repeatedly and stopping transmitting the packet at every time when all processors receive the same packet completely and adding another packet to transmit them. CONSTITUTION:A transmission-side processor 1 transmits plural packets, whose number is equal to the number of flip flops 51-54 of a reception-side processor 4, repeatedly to a data bus. When all flip flops (for example, 51) of individual reception-side processors are set, a control signal goes to '1' through an OR circuit 2, and it is detected thereby that the pertinent packet is received by all reception-side processors, and transmission of the packet is stopped. Data to be transferred next is obtained and is added to another packet as the new packet to start transmission. Thus, the queuing time is shortened in processors having high processing speed in the reception side to improve the operating efficiency.

56. 发明专利

JPS61166651A REPLACING SYSTEM FOR BUFFER MEMORY 失效
公开(公告)号：JPS61166651A
公开(公告)日：1986-07-28
申请号：JP683685
申请日：1985-01-18
申请人： FUJITSU LTD
发明人： TOYOKI NORIYUKI , INOUE KOICHI
IPC分类号： G06F12/12 , G06F12/08
摘要： PURPOSE:To improve the using efficiency of the 2nd buffer memory by securing a certain type of correlation between both replacement actions of the 1st and 2nd buffer memories. CONSTITUTION:A buffer memory LBS of a high speed and small capacity is provided together with a buffer memory MBS of a medium speed and large capacity. When a certain block is replaced for the memory LBS, the address information on a subject block is transmitted to the memory MBS. Here a comparator 38' is set to the memory MBS to detect whether a certain one of blocks to be replaced in the memory MBS includes a transmitted address or not. Then a block to be replaced is decided in the memory MBS. In this case, the block sent from the memory LBS is replaced if it is detected by the comparator 38'. While a block to be replaced is decided by an LRU memory 35 when no block sent from the memory LBS is detected.

57. 发明专利

JPS61138360A Assigning system of processing in compound processor system 失效
标题翻译：化合物处理系统中的处理系统
公开(公告)号：JPS61138360A
公开(公告)日：1986-06-25
申请号：JP26017584
申请日：1984-12-10
申请人： Fujitsu Ltd
发明人： SATO KEIJI , IKESAKA MORIO , INOUE KOICHI
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： G06F15/161
摘要： PURPOSE:To determine simply one processing request processor with a little quantity of hardware and a fine quantity of communication by installing a means to make a processing request by an unanimous broadcasting and a timer means, etc., to set a processing right acquiring signal monitoring period. CONSTITUTION:A processor 3 having a processing request requests the processing from a packet output port 31 through a common communicating channel 4 to processors 1 and 2 by the unanimous broadcasting. The processors 1 and 2 receive a packet by packet input ports 11 and 21, identify a processing request scrambling indication and then, judges whether the processing can be executed or not. As the result, when the processors judge that the processing can be executed, an inherent timer is started. In such a case, when the processor 2 can process, during the inherent action period of a timer 24, an ACK signal monitors whether or not the processor 1 acquires the processing right. When the ACK signal is not detected during the action, the processor 2 acquires the processing right, turns on a processing right acquiring flag holding circuit 25 and process. Thus, by a little quantity of hardware and a fine quantity of com munication, one processing request processor can be easily determined.
摘要翻译：目的：通过安装通过一致广播和定时器等进行处理请求的手段，简单地确定一个具有少量硬件和精细通信量的一个处理请求处理器，以设置处理权获取信号监视期。构成：具有处理请求的处理器3通过一致的广播从处理器1和2请求从分组输出端口31通过公共通信信道4到处理器1和2的处理。处理器1和2通过分组输入端口11和21接收分组，识别处理请求加扰指示，然后判断是否可以执行处理。结果，当处理器判断可以执行处理时，开始固有定时器。在这种情况下，当处理器2能够在定时器24的固有动作期间内处理ACK信号来监视处理器1是否获取处理权限。当在动作期间没有检测到ACK信号时，处理器2获取处理权，打开处理权获取标记保持电路25并进行处理。因此，通过少量的硬件和数量的通信，可以容易地确定一个处理请求处理器。

58. 发明专利

JPS6145647A Access system of multiprocessor system 失效
标题翻译：多处理器系统访问系统
公开(公告)号：JPS6145647A
公开(公告)日：1986-03-05
申请号：JP16679384
申请日：1984-08-09
申请人： Fujitsu Ltd
发明人： SATO KEIJI , IKESAKA MORIO , INOUE KOICHI , ISHII MITSUO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE: To attain freely grouping of processors in a multi-processor system and sharing of functions even after the system is constituted by using an identification information providing broadcast to set freely identification information of a reception processor.
CONSTITUTION: The reception processors #2∼#i are connected to the transmission processor #1 via a bus 2. The processor is constituted by connecting a central processing unit 4, a control storage device 5, a data storage device 6, an interruption control section 7, a broadcast transmission channel 8 and a broadcast reception channel 9 to a CPU bus 3. The identification information is transmitted from the transmission processor #1 to the reception processors, a control means 5 of the reception processor collates the identification with that of the data storage device 6 and when they are concident, required processing is started to the reception processor.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：即使在通过使用提供广播的识别信息构成系统来设置接收处理器的自由识别信息来构成多处理器系统中的处理器的自由分组和功能共享。构成：接收处理器＃2-＃i通过总线2连接到发送处理器＃1。处理器通过连接中央处理单元4，控制存储设备5，数据存储设备6，中断控制部分7，广播传输信道8和广播接收信道9发送到CPU总线3.识别信息从发送处理器＃1发送到接收处理器，接收处理器的控制装置5将标识符与数据存储装置6，并且当它们一致时，对接收处理器开始所需的处理。

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