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51. 发明专利

JP2008027571A Method and memory circuit for operating resistive memory cell 审中-公开
标题翻译：用于操作电阻记忆体的方法和存储器电路
公开(公告)号：JP2008027571A
公开(公告)日：2008-02-07
申请号：JP2007189333
申请日：2007-07-20
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： HOENIGSCHMID HEINZ , MUELLER GERHARD , IVANOV MILENA , CORVIN LIAW
IPC分类号： G11C13/00
CPC分类号： G11C13/0011 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a method for reading memory data from a resistive memory cell including a selection register addressable via a control value. SOLUTION: A controllable selection transistor controlled based on a control value is used. The method includes the step of detecting a cell current flowing through the resistive memory cell, the step of setting the control value depending on the detected cell current, and the step of providing information associated with the control value as memory data. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于从包括经由控制值寻址的选择寄存器的电阻性存储单元读取存储器数据的方法。
解决方案：使用基于控制值控制的可控选择晶体管。该方法包括检测流过电阻式存储单元的单元电流的步骤，根据检测的单元电流设置控制值的步骤以及提供与控制值相关联的信息作为存储器数据的步骤。版权所有（C）2008，JPO＆INPIT

52. 发明专利

JP2007300091A State transition of phase change material caused by annealing 审中-公开
标题翻译：由退火引起的相变材料状态转换
公开(公告)号：JP2007300091A
公开(公告)日：2007-11-15
申请号：JP2007107342
申请日：2007-04-16
申请人： Internatl Business Machines Corp , Qimonda Ag , インターナショナルビジネスマシーンズコーポレイション , キモンダアクチエンゲゼルシャフト
发明人： PHILIPP JAN BORIS , ROSSNAGEL STEPHEN M
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L45/148 , H01L45/06 , H01L45/144 , H01L45/1641
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is adapted so that peeling of a material layer deposited over a phase change material can be prevented, wherein the peeling is caused by such processes that a phase change material is deposited at a low temperature; in a subsequent processing step, the deposited phase change material is heated beyond a crystallization temperature, which causes a transition from an amorphous state to a crystalline state reducing the volume of the phase change material up to about 10%; and the volume reduction causes the peeling of a material layer deposited over a phase change material. SOLUTION: The semiconductor device has a preprocessed wafer 110, and an annealed phase change material layer 118 which is in contact with the preprocessed wafer 110. The semiconductor device has a first material layer 114 which contacts the annealed phase change material layer 118. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其适于使得可以防止在相变材料上沉积的材料层的剥离，其中由相变材料沉积在低温; 在随后的处理步骤中，将沉积的相变材料加热超过结晶温度，其导致从非晶状态转变为结晶状态，从而将相变材料的体积减小至约10％; 并且体积减小导致沉积在相变材料上的材料层的剥离。解决方案：半导体器件具有预处理晶片110和与预处理晶片110接触的退火相变材料层118.半导体器件具有与退火的相变材料层118接触的第一材料层114 版权所有（C）2008，JPO＆INPIT

53. 发明专利

JP2007273962A Phase change memory formed using self-aligned process 审中-公开
标题翻译：使用自对准过程形成的相位变化记忆
公开(公告)号：JP2007273962A
公开(公告)日：2007-10-18
申请号：JP2007051384
申请日：2007-03-01
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： GRUENING VON SCHWERIN ULRIKE , HAPP THOMAS
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a phase change memory formed using a self-aligned process in which a physical memory cell size is scaled down.
SOLUTION: The phase change memory is provided with arrays having a plurality of transistors forming a plurality of rows and columns, first conductive lines forming a plurality of columns, while crossing the arrays, and second conductive lines forming a plurality of rows, while crossing the arrays and encapsulated by dielectric material. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory is provided with phase change elements, between the second conductive lines and contacting the first conductive lines, and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供使用自对准过程形成的相变存储器，其中物理存储单元尺寸按比例缩小。相变存储器设置有具有多个晶体管的阵列，所述多个晶体管形成多个行和列，第一导电线形成多个列，同时跨越阵列，并且第二导线形成多个行，同时穿过阵列并被电介质材料包封。每个第二导线与每行中的晶体管的源极 - 漏极路径的一侧耦合。存储器中设置有相变元件，位于第二导线之间并与第一导线接触并且与第一导线自对准。每个相变元件耦合到晶体管的源 - 漏路径的另一侧。版权所有（C）2008，JPO＆INPIT

54. 发明专利

JP2007243196A Integrated device having multiple chip arrangement and its manufacturing method 审中-公开
标题翻译：具有多个芯片布置的集成设备及其制造方法
公开(公告)号：JP2007243196A
公开(公告)日：2007-09-20
申请号：JP2007058575
申请日：2007-03-08
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： SUBRAYA RAJESH , FISCHER HELMUT , WENNEMUTH INGO , GOSPODINOVA MINKA , THOMAS JOCHEN
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3128 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06551 , H01L2225/06586 , H01L2225/06589 , H01L2225/06596 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for lowering the height of an integrated device in which a plurality of chips are laminated, after sealing with resin.
SOLUTION: The integrated device includes multiple chip arrangements 18 and 24 which are not individually encapusulated in the shape of a capsule. Each of the chip arrangements 18 and 24 has a plurality of connecting elements 16 and 23 for connecting with connecting pads 15 and 21, respectively. The multiple chip arrangements 18 and 24 are mutually laminated so that the connecting elements 16 and 23 may supply electrical coupling to the chip arrangements 18 and 24, respectively. By encapusulating the laminated multiple chip arrangements 18 and 24 in the shape of a capsule, the integrated device with a common perfect mold is obtained.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种降低多层芯片的一体化装置的高度的制造方法，在树脂密封之后。解决方案：集成器件包括多个芯片布置18和24，它们不被单独包封成胶囊的形状。芯片布置18和24中的每一个分别具有多个用于与连接焊盘15和21连接的连接元件16和23。多个芯片布置18和24相互层压，使得连接元件16和23可以分别向芯片布置18和24提供电耦合。通过将层叠的多个芯片布置18和24包封成胶囊的形状，获得具有共同的完美模具的集成装置。版权所有（C）2007，JPO＆INPIT

55. 发明专利

JP2007243169A Phase change memory cell having heat insulation mechanism 审中-公开
标题翻译：具有热绝缘机制的相变存储器单元
公开(公告)号：JP2007243169A
公开(公告)日：2007-09-20
申请号：JP2007028023
申请日：2007-02-07
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： GRUENING VON SCHWERIN ULRIKE , HAPP THOMAS , PHILIPP JAN BORIS
IPC分类号： H01L27/105
CPC分类号： H01L45/06 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/1226 , H01L45/1233 , H01L45/128 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a phase change memory cell having heat insulating materials for memory cell resistive elements and a heat dissipating means for thermally insulating each memory cell from others, to prevent a thermal cross-talk and improve data retention characteristics at high temperatures. SOLUTION: A memory array 100a has phase change memory cells 104, first heat insulating materials 120 and a second heat insulating material 122. Each memory element 106 is surrounded by the first heat insulating material 120 which has a low heat conductivity to insulate each memory cell 104 thermally from others. The second heat insulating material 122 is laid in between the memory cells 104 while contacting the first heat insulating materials 120. Because the second heat insulating material 122 contains dielectric material having a heat conductivity higher than the first heat insulating material 120, any heat that leaks through the first heat insulating materials 120 placed around the memory cells 104 is quickly dissipated. Combining heat insulation and heat dissipation allows adjacent phase change memory cells 104 to be kept at a lower temperature during reset operation. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有用于存储单元电阻元件的绝热材料的相变存储单元和用于将每个存储单元与其他绝缘体隔热的散热装置，以防止热串扰并提高数据保持特性在高温下。存储器阵列100a具有相变存储单元104，第一绝热材料120和第二绝热材料122.每个存储元件106被第一绝热材料120包围，该第一绝热材料120具有低导热性以绝缘每个存储单元104与其他存储单元104热热。第二绝热材料122与第一绝热材料120接触而放置在存储单元104之间。由于第二绝热材料122包含导热率高于第一绝热材料120的电介质材料，因此泄漏的任何热量通过放置在存储单元104周围的第一绝热材料120被快速消散。结合绝热和散热，允许相邻的相变存储单元104在复位操作期间保持在较低的温度。版权所有（C）2007，JPO＆INPIT

56. 发明专利

JP2007184598A Method for forming integrated circuit on semiconductor substrate 审中-公开
标题翻译：在半导体基板上形成集成电路的方法
公开(公告)号：JP2007184598A
公开(公告)日：2007-07-19
申请号：JP2006349899
申请日：2006-12-26
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： HECHT THOMAS , BERNHARDT HENRY , KAPTEYN CHRISTIAN
IPC分类号： H01L23/52 , H01L21/20 , H01L21/28 , H01L21/3205 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/423 , H01L29/49
CPC分类号： H01L29/4925 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02513 , H01L21/02532 , H01L21/02667 , H01L21/28044 , H01L21/823437 , H01L21/823828 , H01L27/0629 , H01L27/10861 , H01L27/10873 , H01L29/66181
摘要： PROBLEM TO BE SOLVED: To solve the problem of distortion of a substrate due to phase change of an amorphous silicon layer when forming a polycrystal silicon layer that is used for wiring, by reducing the deformation by avoiding occurrence of mechanical stress at phase change.
SOLUTION: An amorphous anti-stress layer 3 is provided, as an intermediate layer, on a conductive layer 2 such as a capacitor electrode and a gate electrode on a substrate 1, and an amorphous silicon layer 4 is formed over it. Then it is heated to the crystallizing temperature of the silicon layer so that the amorphous silicon layer is phase-changed to provide a polycrystal silicon layer. Thanks to presence of the anti-stress layer, occurrence of mechanical stress when crystallizing is avoided. The anti-stress layer is phase-changed for a lower resistance by separate heating, so that the conductive layer and the polycrystal silicon layer are electrically connected together.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了解决当形成用于布线的多晶硅层时由于非晶硅层的相变导致的衬底失真的问题，通过避免在相位发生机械应力而减小变形更改。解决方案：在诸如电容器电极的导电层2和基板1上的栅极电极上提供作为中间层的非晶形抗应力层3，并且在其上形成非晶硅层4。然后将其加热到硅层的结晶温度，使得非晶硅层相变以提供多晶硅层。由于抗应力层的存在，避免了当结晶时发生机械应力。通过单独加热，抗应力层通过较低的电阻相变，使得导电层和多晶硅层电连接在一起。版权所有（C）2007，JPO＆INPIT

57. 发明专利

JP2007128632A Maintaining internal voltage of integrated circuit in response to clocked standby mode 审中-公开
标题翻译：集成电路的内部电压响应时钟待机模式
公开(公告)号：JP2007128632A
公开(公告)日：2007-05-24
申请号：JP2006210182
申请日：2006-08-01
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： ALEXANDER GEORGE WILLIAM , HEILMANN BEN , HERBERT DAVID
IPC分类号： G11C11/4074 , G05F1/10 , G05F3/02 , G06F1/26 , G11C11/413
CPC分类号： G11C5/147
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for controlling an output reference voltage generated by a reference voltage generator arranged on a memory device. SOLUTION: A signal for enabling a clocked standby mode of a memory device is received. When this signal indicates that the above memory device is in the clocked standby mode, a first reference voltage is generated as an output reference voltage of the above reference voltage generator by using the first voltage. When the above signal indicates that the above memory device is not in a clocked standby mode, a second reference voltage is generated as an output reference voltage of the above reference voltage generator by using the second voltage. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于控制由布置在存储器件上的参考电压发生器产生的输出参考电压的方法和装置。
解决方案：接收用于启用存储器设备的时钟待机模式的信号。当该信号指示上述存储器件处于时钟待机模式时，通过使用第一电压，产生第一参考电压作为上述参考电压发生器的输出参考电压。当上述信号指示上述存储器件未处于计时待机模式时，通过使用第二电压产生第二参考电压作为上述参考电压发生器的输出基准电压。版权所有（C）2007，JPO＆INPIT

58. 发明专利

JP2007115394A Specified auto-refresh for dynamic random access memory 审中-公开
标题翻译：用于动态随机存取存储器的指定自动刷新
公开(公告)号：JP2007115394A
公开(公告)日：2007-05-10
申请号：JP2006281725
申请日：2006-10-16
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： FREEBERN MARGARET C
IPC分类号： G11C11/406
CPC分类号： G11C8/12 , G11C8/04 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40622 , G11C11/4087
摘要： PROBLEM TO BE SOLVED: To provide a specified auto-refresh mode for executing specified auto-refresh in an active state where another memory bank accesses one memory bank to execute read/write. SOLUTION: The memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a row address counter 126 configured to provide a row address for selecting a row of memory cells for a directed auto-refresh, and a bank address counter 136 configured to provide a bank address for selecting one of at least two memory banks for a specified auto-refresh. The bank address counter is implemented as least significant bits of the row address counter. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供指定的自动刷新模式，用于在另一个存储体访问一个存储体以执行读/写的活动状态下执行指定的自动刷新。解决方案：存储器包括至少两个存储体，每个存储体包括包括行和列的存储单元阵列。存储器包括行地址计数器126，其被配置为提供用于选择用于定向自动刷新的存储器单元的行的行地址，以及存储体地址计数器136，其被配置为提供用于选择至少两个存储体中的一个的存储体地址，用于指定的自动刷新。银行地址计数器被实现为行地址计数器的最低有效位。版权所有（C）2007，JPO＆INPIT

59. 发明专利

JP2007110128A Semiconductor structure including premetal dielectric and method of forming premetal dielectric in semiconductor structure 审中-公开
标题翻译：包括电介质的半导体结构及其在半导体结构中形成电介质的方法
公开(公告)号：JP2007110128A
公开(公告)日：2007-04-26
申请号：JP2006277917
申请日：2006-10-11
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： DITTKRIST THOMAS , JAHNE STEFFEN , DAS ARABINDA
IPC分类号： H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L21/76837 , H01L21/76834
摘要： PROBLEM TO BE SOLVED: To provide: a semiconductor structure including a premetal dielectric; and the method of carrying out deposition of the premetal dielectric in the semiconductor structure.
SOLUTION: The semiconductor structure includes a substrate 1 with each constituent element 2, 3, 4, 9, and 11 on the surface. Each constituent element 2, 3, 4, 9, and 11 are spaced apart from one another so that at least one gap is formed. The gap is filled with the advantageous combination of a layer. The combination includes the layer of a dielectric 14 for spin-on formation at least. Further, a semiconductor structure includes a premetal dielectric in which another insulating film is arranged or a silicate glass layer 16 is arranged in which phosphorus is doped. The use of the combination of each layer suppresses or prevents the occurrence of a void 17 in the filling of the gap. In the semiconductor structure, each property is obtained which is chemically and/or mechanically, and/or electronically advantageous.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供：包括前金属电介质的半导体结构; 以及在半导体结构中进行前金属电介质的沉积的方法。解决方案：半导体结构包括具有表面上的每个构成元件2,3,4,9和11的衬底1。每个构成元件2,3,4,9和11彼此间隔开，使得形成至少一个间隙。间隙充满了层的有利组合。该组合包括至少用于旋转形成的电介质层14。此外，半导体结构包括其中布置另一绝缘膜的前金属电介质或其中掺杂有磷的硅酸盐玻璃层16。使用各层的组合抑制或防止间隙填充中出现空隙17。在半导体结构中，获得化学和/或机械和/或电子有利的每种性质。版权所有（C）2007，JPO＆INPIT

60. 发明专利

JP2007019493A Method of forming contact in flash memory device 审中-公开
标题翻译：在闪存存储器件中形成接触的方法
公开(公告)号：JP2007019493A
公开(公告)日：2007-01-25
申请号：JP2006170071
申请日：2006-06-20
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： OLLIGS DOMINIK , NAGEL NICOLAS
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a method of increasing the effective overlapping amount when forming a contact between a bit line and local wiring in a flash memory device. SOLUTION: A method comprises a process of forming a hard mask layer on a planarized surface including an exposed top of local wiring prior to depositing an oxide dielectric layer. Openings in the hard mask 18 define positions of contacts with the local wiring of the exposed top. An etch mask is formed on an interlayer insulation layer to define bit line trenches. Anisotropic etching or the like is performed down to the top of the local wiring through the openings in the hard mask 18. In this process, the contacts are established only through overlaps between the openings in the hard mask and openings in the etch mask layer. In particular, the formed bit line trenches have a uniform width and uniform spacing to adjacent bit lines because connection holes are formed only directly beneath the etch mask that defines the bit lines. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在闪速存储器件中形成位线和局部布线之间的接触时增加有效重叠量的方法。解决方案：一种方法包括在沉积氧化物介电层之前在包括局部布线的暴露顶部的平坦化表面上形成硬掩模层的工艺。硬掩模18中的开口限定与暴露顶部的局部布线的触点位置。在层间绝缘层上形成蚀刻掩模以限定位线沟槽。各向异性蚀刻等通过硬掩模18中的开口向下到达局部布线的顶部。在该过程中，仅通过硬掩模中的开口和蚀刻掩模层中的开口之间的重叠来建立触点。特别地，形成的位线沟槽具有与相邻位线的均匀宽度和均匀的间隔，因为连接孔仅形成在限定位线的蚀刻掩模下方。版权所有（C）2007，JPO＆INPIT

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