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1. 发明专利

JP2007019493A Method of forming contact in flash memory device 审中-公开
标题翻译：在闪存存储器件中形成接触的方法
公开(公告)号：JP2007019493A
公开(公告)日：2007-01-25
申请号：JP2006170071
申请日：2006-06-20
申请人： Qimonda Ag , キモンダアクチエンゲゼルシャフト
发明人： OLLIGS DOMINIK , NAGEL NICOLAS
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a method of increasing the effective overlapping amount when forming a contact between a bit line and local wiring in a flash memory device. SOLUTION: A method comprises a process of forming a hard mask layer on a planarized surface including an exposed top of local wiring prior to depositing an oxide dielectric layer. Openings in the hard mask 18 define positions of contacts with the local wiring of the exposed top. An etch mask is formed on an interlayer insulation layer to define bit line trenches. Anisotropic etching or the like is performed down to the top of the local wiring through the openings in the hard mask 18. In this process, the contacts are established only through overlaps between the openings in the hard mask and openings in the etch mask layer. In particular, the formed bit line trenches have a uniform width and uniform spacing to adjacent bit lines because connection holes are formed only directly beneath the etch mask that defines the bit lines. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在闪速存储器件中形成位线和局部布线之间的接触时增加有效重叠量的方法。解决方案：一种方法包括在沉积氧化物介电层之前在包括局部布线的暴露顶部的平坦化表面上形成硬掩模层的工艺。硬掩模18中的开口限定与暴露顶部的局部布线的触点位置。在层间绝缘层上形成蚀刻掩模以限定位线沟槽。各向异性蚀刻等通过硬掩模18中的开口向下到达局部布线的顶部。在该过程中，仅通过硬掩模中的开口和蚀刻掩模层中的开口之间的重叠来建立触点。特别地，形成的位线沟槽具有与相邻位线的均匀宽度和均匀的间隔，因为连接孔仅形成在限定位线的蚀刻掩模下方。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007103920A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007103920A
公开(公告)日：2007-04-19
申请号：JP2006232929
申请日：2006-08-30
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： MUELLER THORSTEN , STEFANO PARASCANDOLA , OLLIGS DOMINIK , RIEDEL STEPHAN , KNOEFLER ROMAN , CASPARY DIRK
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a method of suitably forming contacts on buried bit lines. SOLUTION: Bit lines (10) are formed by implanting dopants by means of a sacrificial hard mask layer. The hard mask layer is later replaced with gate electrodes made of polysilicon in a memory cell array. Striplike areas of the memory cell array extending transversely across the bit lines are reserved by a blocking layer (11) to be occupied by bit line contacts. In these areas, the hard mask (5) is used to form contact holes (13) which are self-aligned with the implanted buried bit lines. Between the blocked areas, word lines are arranged perpendicular to the bit lines. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在掩埋位线上适当地形成接触的方法。解决方案：通过牺牲硬掩模层注入掺杂剂形成位线（10）。硬掩模层随后由存储单元阵列中由多晶硅制成的栅电极代替。跨越位线横向延伸的存储单元阵列的带状区域由阻挡层（11）保留以被位线接触占据。在这些区域中，硬掩模（5）用于形成与注入的掩埋位线自对准的接触孔（13）。在阻塞区域之间，字线垂直于位线布置。版权所有（C）2007，JPO＆INPIT

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