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    • 47. 发明专利
    • COLOR ENCODER
    • JPH04168481A
    • 1992-06-16
    • JP29363090
    • 1990-11-01
    • RICOH KK
    • MAEDA HIDEKAZUSAKAGAMI HIROFUMITANAKA MASABUMI
    • H04N11/14G09G5/04H04N9/65
    • PURPOSE:To make a device compact, and reduce a cost by making two input color signal correspond to each ROM for performing the balanced modulation digitally, and inputting address synchronized with the color signal, and adding the modulated output of both the two ROM, and thereafter, eliminating unnecessary component with BPF. CONSTITUTION:The feedback erasing period data 0 and the data A of a burst level are added to the digital color signal R - Y, B - Y by switching switches 12, 13, 14 with a predetermined method. An address generator 17 counts sampling clock CLK, and outputs an address corresponding to ROM 15, 16, namely, a coefficient of the color sub-carrying wave of cosine and sine component. The reset pulse RST is input to the address generator 17, and this address is reset to be synchronized with the color signal. Next, each balanced modulation output of the ROM 15, 16 is added by a computer 18, and thereafter, unnecessary frequency component is eliminated by BPF 19 to obtain the digital color encoded output. A device is thereby made compact and a cost is reduced.
    • 49. 发明专利
    • IMAGE PICKUP DEVICE
    • JPH03273786A
    • 1991-12-04
    • JP7184990
    • 1990-03-23
    • CANON KK
    • NINOMIYA KUNIO
    • H04N5/232H04N5/335H04N5/372H04N5/378H04N9/65H04N11/16
    • PURPOSE:To stably output a sub carrier and a burst signal without affecting the frequency of the second reference frequency signal with the frequency change of the first reference frequency by canceling the PLL control of the first and second reference frequency signals at the time of an external synchronizing mode. CONSTITUTION:In the case of the external synchronizing mode, an external synchronizing signal input discriminating circuit 11 detects that an external synchronizing signal is inputted from an input terminal 20, the voltage value of a signal line 15 is turned to a constant value and the frequency to be outputted from an Nfsc oscillator 10 is forcibly fixed. When the control voltage of the signal line 15 reaches a certain constant value, the Nfsc oscillator 10 to output an Nfsc clock signal is stably oscillated with the frequency Nfsc at the frequency of the voltage value. Thus, when the frequency Nfsc is stablized, the frequencies of the sub carrier and the burst signal to be outputted from a sub carrier burst generating circuit and a PLL circuit 8 are made stable as well.