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41. 发明专利

JP3264142B2 失效
公开(公告)号：JP3264142B2
公开(公告)日：2002-03-11
申请号：JP14167295
申请日：1995-06-08
IPC分类号： H03H21/00 , H04B3/06 , H04L7/02 , H04L7/027 , H04L7/033 , H04L7/04 , H04L7/10 , H04L27/22 , H04L27/38

42. 发明专利

JP2002044064A RADIO EQUIPMENT FOR MOBILE STATION, RADIO EQUIPMENT FOR FIXED STATION AND WIRELESS COMMUNICATION SYSTEM 失效
公开(公告)号：JP2002044064A
公开(公告)日：2002-02-08
申请号：JP2000224365
申请日：2000-07-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ASANUMA TSUTOMU , SHIRAISHI SATOSHI , HANAWA TAKESHI
IPC分类号： H04L27/22 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To compensate the influence of an environmental fluctuation in temperature or the like, to keep constant frequency characteristics or delay quantity and to switch the Q value of a resonance selecting part at the rise time of a frame and the pull-in time of a clock in radio equipment for performing receiving demodulation while using a regenerated clock. SOLUTION: A resonance selecting part 4 selects a regenerated clock frequency and a delay part 5 controls timing to extract an I or Q signal in an A/D converter 3. The temperature of the device is detected by an environmental fluctuation detecting part 8 and a control part 6 reads a correction value corresponding to this detected temperature of the device out of a correction value storage part 7. The correction value storage part 7 stores a correction value for compensating the frequency characteristics of the resonance selecting part 4 and the control part 6 compensates and controls the frequency characteristics of the resonance selecting part 4 to compensate the fluctuation. Thus, even when the environmental state of the device is fluctuated, the fixed frequency characteristics can be kept at all the time and receiving performance can be stabilized.

43. 发明专利

JP2001298419A OPTICAL SPACE TRANSMITTER 失效
公开(公告)号：JP2001298419A
公开(公告)日：2001-10-26
申请号：JP2000114901
申请日：2000-04-17
申请人： CANON KK
发明人： SHIGETA JUNJI
IPC分类号： H04B10/07 , H04B10/077 , H04B10/079 , H04B10/11 , H04B10/112 , H04B10/556 , H04B17/00 , H04L7/027 , H04B10/105 , H04B10/00 , H04B10/08 , H04B10/10 , H04B10/22
摘要： PROBLEM TO BE SOLVED: To provide an optical space transmitter that can quickly detect a fault location. SOLUTION: A main signal in the transmitter 1 is combined with an auxiliary signal, the combined signal is converted into an optical signal via a laser diode 8 and outputted to an opposite receiver 2, and converted into an electric signal at a photoelectric conversion section 15 via lenses 12, 13, 14 of the receiver 2. The auxiliary signal component is extracted from this electrical signal and outputted to a CPU 25. Since the level of the auxiliary signal from the transmitter 1 is kept constant, when a DC component level of the received optical signal is increased/decreased, the level of the auxiliary signal is increased/decreased in proportion to the increase/ decrease. Furthermore, the main signal component is extracted from the electric signal and outputted to the CPU 25, and a clock is extracted from the electrical signal and information, denoting whether synchronization is taken, is outputted to the CPU 25. Since the CPU 25 extracts the DC component level, an AC component level and the clock component from the data signal and analyzes the information and displays the respective states, or the information of the fault location obtained from the respective states or the both on a display section 26, a user can recognize the fault state, on the basis of this information.

44. 发明专利

JP2001292179A SIGNAL INTERRUPT DETECTION CIRCUIT, COMMUNICATION CLOCK REPRODUCING DEVICE AND DATA REPRODUCING DEVICE INCORPORATING THE CIRCUIT 失效
公开(公告)号：JP2001292179A
公开(公告)日：2001-10-19
申请号：JP2000107816
申请日：2000-04-10
申请人： SUMITOMO METAL MINING CO
发明人： YAMANOBE YASUNARI
IPC分类号： G06F1/04 , G06F1/12 , H04L7/027 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide a signal interrupt detection circuit with an improved signal interrupt and resetting speed, a communication clock reproducing device and a data reproducing device incorporating this circuit. SOLUTION: The signal interrupt detection circuit to be incorporated into a communication clock reproducing device provided with a two-multiplication circuit 1, a clock extraction filter 2, a limiting amplifier circuit 3 and a phase adjusting circuit 4 or into a data reproducing device provided with a discrimination circuit 5, in addition to the clock extraction filter and the circuits mentioned above uses loss output obtained by comparing an envelope amplitude signal obtained by envelope-detecting a basic clock component which is extracted by filtering a signal from the two-multiplication circuit with a quasi- narrow band pass filter 11 having a frequency selection degree lower than the frequency selection degree (Q value) of the clock extraction filter by an envelope detection circuit 12 with a fixed threshold by a comparator circuit 13.

45. 发明专利

JP3218113B2 失效
公开(公告)号：JP3218113B2
公开(公告)日：2001-10-15
申请号：JP5377593
申请日：1993-03-15
IPC分类号： H04L7/00 , H04L7/027 , H04L27/22

46. 发明专利

JP2001268061A BIT SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JP2001268061A
公开(公告)日：2001-09-28
申请号：JP2000081167
申请日：2000-03-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ONODERA KIYOMITSU
IPC分类号： H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide a bit synchronization circuit that can have no dead band phase, instantaneously establish synchronization, and can be in operation even at a high-speed bit rate of 10 Gb/s or over. SOLUTION: The bit synchronization circuit of this invention is characterized in that a phase and an amplitude of a data signal are compared with those of a reference clock signal to instantaneously establish bit synchronization, the circuit is configured with a simple logic, the bit synchronization is instantaneously established because of absence of a feedback loop, the phase of the data signal is analogically compared with the phase of the clock signal, and sampling and holding the result of the phase comparison receives no limitation of a preamble pattern.

47. 发明专利

JP3186665B2 失效
公开(公告)号：JP3186665B2
公开(公告)日：2001-07-11
申请号：JP25564797
申请日：1997-09-19
IPC分类号： H04L27/22 , H04L7/00 , H04L7/027

48. 发明专利

JP2001506079A 失效
公开(公告)号：JP2001506079A
公开(公告)日：2001-05-08
申请号：JP52627098
申请日：1997-12-12
IPC分类号： H04L7/06 , H04B7/26 , H04L7/027 , H04L7/04

49. 发明专利

JP2001506016A 失效
公开(公告)号：JP2001506016A
公开(公告)日：2001-05-08
申请号：JP53991698
申请日：1998-03-16
IPC分类号： G02F1/35 , H01S3/098 , H04B10/2507 , H04L7/027 , H04B10/02

50. 发明专利

JP2001103118A ASYNCHRONOUS DATA RECEPTION INTERFACE CIRCUIT 失效
公开(公告)号：JP2001103118A
公开(公告)日：2001-04-13
申请号：JP27968499
申请日：1999-09-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ISHIZUKA KAZUTOSHI
IPC分类号： H04L29/08 , H04L7/00 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To provide an asynchronous data reception interface circuit that can surely capture data independently of a clock speed or phase in asynchronous data communication. SOLUTION: A request storage flip-flop 40 is inserted between a request latch flip-flop 21 operated synchronously with a transmission clock and a request recognition flip-flop 25 operated synchronously with a clock at a receiver side circuit. Then this request storage flip-flop 40 is operated by an inverse of the transmission clock or of the receiver side clock. Thus, a timing delay by a half period is produced to ensure a sufficient data capture period.

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