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41. 发明专利

JP2013134792A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013134792A
公开(公告)日：2013-07-08
申请号：JP2011284154
申请日：2011-12-26
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HIRAISHI ATSUSHI , KANNO TOSHIO , NARUI SEIJI , TAKAI YASUHIRO
IPC分类号： G11C11/401 , G11C11/4076 , G11C11/4093
CPC分类号： G11C7/222 , G11C7/1057 , G11C7/1066
摘要： PROBLEM TO BE SOLVED: To perform an ODT operation properly even when input timing of a data signal and a data strobe signal is offset.SOLUTION: A semiconductor device comprises: data strobe terminals 17a and 17b; output drivers 218 and 219 respectively connected to data strobe terminals 17a and 17b; data terminals 16-0 to 16-7; output drivers 210 to 217 respectively connected to the data terminals 16-0 to 16-7; and a data control circuit 100 that, in response to ODT control command ODTcontA, causes the output drivers 218 and 219 and the output drivers 210 to 217 to function as termination resistors at a different timing from each other. According to the present invention, the value of the termination resistor does not change during reception of a data signal DQ even when a reception timing of the data signal DQ and that of a data strobe signal DQS are offset in write operation.
摘要翻译：要解决的问题：即使当数据信号和数据选通信号的输入定时被偏移时也能适当地执行ODT操作。解决方案：半导体器件包括：数据选通端子17a和17b; 分别连接到数据选通端子17a和17b的输出驱动器218和219; 数据终端16-0至16-7; 分别连接到数据端子16-0至16-7的输出驱动器210至217; 以及数据控制电路100，其响应于ODT控制命令ODTcontA使得输出驱动器218和219以及输出驱动器210至217在彼此不同的定时用作终端电阻器。根据本发明，即使数据信号DQ的接收定时和数据选通信号DQS的接收定时在写入操作中被偏移，终端电阻的值也不会在接收数据信号DQ期间改变。

42. 发明专利

JP2013131282A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013131282A
公开(公告)日：2013-07-04
申请号：JP2011282345
申请日：2011-12-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KURIHARA KAZUHIRO , ISHIKAWA TORU
IPC分类号： G11C29/12
摘要： PROBLEM TO BE SOLVED: To capture read data read by a usual read operation using a boundary scan function.SOLUTION: A semiconductor device comprises at least one memory chip, the memory chip including: a plurality of data input/output terminals 35 each for inputting write data or outputting read data; a boundary scan unit BSU having a plurality of IO units IOU each connected to each of the data input/output terminals 35 and boundary wiring Lb connecting each of the IO units IOU to form a cascade connection; and a serial data output terminal 72 for outputting serial data from the IO units IOU through the boundary wiring Lb. The boundary scan unit BSU provides a parallel output of read data read from a memory cell array for the data input/output terminals and receives again read data appearing at the data input/output terminals to latch the read dada at a predetermined timing. Then, the boundary scan unit BSU provides a serial output from a serial data output terminal.
摘要翻译：要解决的问题：捕获通过使用边界扫描功能的通常读取操作读取的读取数据。解决方案：半导体器件包括至少一个存储器芯片，该存储器芯片包括：多个数据输入/输出端子35，每个用于输入写数据或输出读数据; 边界扫描单元BSU，其具有连接到每个数据输入/输出端子35的多个IO单元IOU和连接每个IO单元IOU以形成级联连接的边界布线Lb; 以及串行数据输出端子72，用于通过边界线路Lb从IO单元IOU输出串行数据。边界扫描单元BSU提供从用于数据输入/输出端子的存储单元阵列读取的读取数据的并行输出，并再次接收在数据输入/输出端子处出现的读取数据，以在预定定时锁存读取的数据。然后，边界扫描单元BSU从串行数据输出端子提供串行输出。

43. 发明专利

JP2013131278A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2013131278A
公开(公告)日：2013-07-04
申请号：JP2011281929
申请日：2011-12-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NOMOTO KEISUKE , NAKAOKA YUJI
IPC分类号： G11C11/4074
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C11/4074 , G11C11/4094 , G11C11/4097 , G11C16/30 , G11C2207/005 , G11C2207/2227
摘要： PROBLEM TO BE SOLVED: To reduce power consumption by power down while reducing a chip area.SOLUTION: A semiconductor memory device includes a memory cell array 5 including a plurality of memory cells, a peripheral circuit 401 connected to the memory cell array by a plurality of input/output lines MAIN-IO(T/B), and a power supply circuit 501, 601 which supplies an operation voltage to the memory cell array 5 and the peripheral circuit 401 during normal operation mode, and stops the supply of the operation voltage to the memory cell array without stopping the supply of the operation voltage to the peripheral circuit 401 during power down mode.
摘要翻译：要解决的问题：通过降低芯片面积来降低掉电的功耗。解决方案：半导体存储器件包括包括多个存储单元的存储单元阵列5，通过多个连接到存储单元阵列的外围电路401 的输入/输出线MAIN-IO（T / B）和在正常操作模式期间向存储单元阵列5和外围电路401提供操作电压的电源电路501,601，并且停止提供操作电压到存储单元阵列，而不会在断电模式期间停止向外围电路401提供工作电压。

44. 发明专利

JP2013131262A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013131262A
公开(公告)日：2013-07-04
申请号：JP2011278558
申请日：2011-12-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAJITANI KAZUHIKO
IPC分类号： G11C11/4096 , G11C11/401
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4097 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of appropriate switch control using a differential local sense amplifier and a single-ended global bit line in a memory cell array having an open bit line structure.SOLUTION: A semiconductor device of the present invention comprises: a pair of local bit lines LBLL and LBLR that are selectively connected with a plurality of memory cells MC; a differential local sense amplifier LSA that amplifies a difference voltage thereof; a global bit line GBL; and a pair of switches Q10 and Q11 that are connected between the local bit lines LBLL and LBLR and the global bit line GBL. Write data to the memory cells MC on the local bit line LBLL side is transmitted from the global bit line GBL to the local bit line LBLL via the switch Q10. Write data to the memory cells MC on the local bit line LBLR side is transmitted from the global bit line GBL to the local bit line LBLR via the switch Q11.
摘要翻译：要解决的问题：提供一种能够在具有开放位线结构的存储单元阵列中使用差分局部读出放大器和单端全局位线的适当开关控制的半导体器件。解决方案：本发明的半导体器件包括：与多个存储单元MC选择性地连接的一对局部位线LBLL和LBLR; 差分局部读出放大器LSA，放大其差电压; 全局位线GBL; 以及连接在本地位线LBLL和LBLR与全局位线GBL之间的一对开关Q10和Q11。向本地位线LBLL侧的存储单元MC写入数据经由开关Q10从全局位线GBL发送到本地位线LBLL。向本地位线LBLR侧的存储单元MC写入数据经由开关Q11从全局位线GBL发送到本地位线LBLR。

45. 发明专利

JP2013125955A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013125955A
公开(公告)日：2013-06-24
申请号：JP2011275943
申请日：2011-12-16
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TONARI KAZUAKI
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L28/40 , H01L27/10852
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same, capable of reducing a leak current of a capacitor, suppressing peeling of a tungsten film constituting an upper electrode formed in a laminated structure, and reducing specific resistance of the upper electrode.SOLUTION: A semiconductor device includes a capacitor 12 provided on a semiconductor substrate 11. An upper electrode 15 constituting the capacitor 12 includes a laminated structure in which a doped polysilicon germanium film 18, a doped polysilicon film 19, and a tungsten film 21 are sequentially laminated.
摘要翻译：要解决的问题：为了提供一种半导体器件及其制造方法，能够减小电容器的漏电流，抑制构成层叠结构中形成的上电极的钨膜的剥离，上电极的电阻。解决方案：半导体器件包括设置在半导体衬底11上的电容器12.构成电容器12的上电极15包括其中掺杂多晶硅锗18，掺杂多晶硅膜19和钨膜 21依次层压。版权所有（C）2013，JPO＆INPIT

46. 发明专利

JP2013120474A Arithmetic device 审中-公开
标题翻译：算术设备
公开(公告)号：JP2013120474A
公开(公告)日：2013-06-17
申请号：JP2011267691
申请日：2011-12-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： YAMAGUCHI TOSHIHIRO
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To constitute a high-capacity LR/RDIMM by using a low-cost DIMM without requiring a large scale device for using an elaborate bonding wire technique.SOLUTION: An arithmetic device includes a mother board mounting a first memory controller and an interposer board connected to the mother board and mounting a DIMM and a second memory controller. The first memory controller repeatedly changes an input/output state of a signal between itself and the second memory controller, and the second memory controller repeatedly changes an input/output state of a signal between itself and the DIMM. The device includes a control unit for determining whether data written in the DIMM can be correctly read or not every time the input/output state changes, and on the basis of the determination result, optimizing the input/output state of the signal between the first memory controller and the second memory controller and the input/output state of the signal between the second memory controller and the DIMM.
摘要翻译：要解决的问题：通过使用低成本的DIMM来构成高容量LR / RDIMM，而不需要使用精细的接合线技术的大规模器件。解决方案：运算装置包括安装第一存储器控制器的主板和连接到母板的插入板，并安装DIMM和第二存储器控制器。第一存储器控制器重复地改变其本身和第二存储器控制器之间的信号的输入/输出状态，并且第二存储器控制器重复地改变其本身与DIMM之间的信号的输入/输出状态。该装置包括控制单元，用于在每次输入/输出状态改变时确定写入DIMM中的数据是否能被正确读取，并且基于该确定结果，优化第一和第二数据之间的信号的输入/输出状态存储器控制器和第二存储器控制器以及第二存储器控制器和DIMM之间的信号的输入/输出状态。版权所有（C）2013，JPO＆INPIT

47. 发明专利

JP2013118264A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013118264A
公开(公告)日：2013-06-13
申请号：JP2011264630
申请日：2011-12-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIYAZAKI TORU
IPC分类号： H01L23/12 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same, having a contact point structure being excellent in junction strength with less resistance, relating to a terminal part connection of a through electrode in which solder junction is used.SOLUTION: A layer containing gold is not formed on a terminal surface to be joined to a solder layer, and instead, a hydrogen plasma treatment is performed, for removing an oxide film and performing reform to provide a film which is hard to be re-oxidized. More specifically, the manufacturing method includes the steps of: forming a through electrode structure 21 that penetrates a substrate in the thickness direction; performing a hydrogen plasma treatment on a Ni layer 10 on a first surface of the through electrode structure 21 which is exposed on one main surface of the substrate; and forming a solder film 20 on a second surface of the through electrode structure 21 which is exposed on the other main surface of the substrate.
摘要翻译：要解决的问题：为了提供一种半导体器件及其制造方法，具有接触点结构优异的接合强度和较小电阻，涉及其中焊接结是通孔电极的端子部分连接用过的。解决方案：在要与焊料层接合的端子表面上不形成含有金的层，而是进行氢等离子体处理，用于除去氧化膜并进行改性以提供难以被再次氧化。更具体地说，制造方法包括以下步骤：形成在厚度方向上穿透基板的贯通电极结构体21。在通过电极结构21的暴露在基板的一个主表面上的第一表面上的Ni层10上进行氢等离子体处理; 在通孔电极结构体21的露出在基板的另一个主面上的第二面上形成焊锡膜20。版权所有（C）2013，JPO＆INPIT

48. 发明专利

JP2013118258A Semiconductor wafer, semiconductor device, and method for manufacturing the same 审中-公开
标题翻译：半导体晶体管，半导体器件及其制造方法
公开(公告)号：JP2013118258A
公开(公告)日：2013-06-13
申请号：JP2011264523
申请日：2011-12-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NAKAE MINORU
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress generation of cracks by dispersing a stress generated in an insulating film on a second groove.SOLUTION: The method includes steps of: forming first and second annular grooves on a fist main surface of a substrate; then forming an insulating film on the substrate so as to fill the first and second grooves; forming a mask pattern so that a mask is positioned on the insulating film on the first groove and a plurality of divided masks are positioned on the insulating film on the second groove; removing the insulating film by etching using the mask pattern so that the first main surface of the substrate is not exposed; removing the insulating film on the first main surface and then forming a photoresist film on the first main surface of the substrate; transferring a first pattern which has been aligned with a position on the substrate of the second groove filled with the insulating film as a reference, onto the photoresist film; and forming a through electrode on the substrate positioned inside of the first annular groove filled with the insulating film.
摘要翻译：要解决的问题：通过将在绝缘膜中产生的应力分散在第二凹槽上来抑制裂纹的产生。解决方案：该方法包括以下步骤：在基板的第一主表面上形成第一和第二环形槽; 然后在基板上形成绝缘膜以便填充第一和第二槽; 形成掩模图案，使得掩模位于第一凹槽上的绝缘膜上，并且多个分割的掩模位于第二凹槽上的绝缘膜上; 通过使用掩模图案的蚀刻去除绝缘膜，使得基板的第一主表面不被暴露; 去除第一主表面上的绝缘膜，然后在基板的第一主表面上形成光致抗蚀剂膜; 将与填充有绝缘膜的第二槽的基板上的位置对准的第一图案作为基准转印到光致抗蚀剂膜上; 以及在位于填充有绝缘膜的第一环形槽内侧的基板上形成贯通电极。版权所有（C）2013，JPO＆INPIT

49. 发明专利

JP2013115382A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013115382A
公开(公告)日：2013-06-10
申请号：JP2011262946
申请日：2011-11-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TORII YASUSHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/7682 , H01L21/76898 , H01L23/3135 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/0401 , H01L2224/05571 , H01L2224/11002 , H01L2224/1146 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/14156 , H01L2224/14181 , H01L2224/16146 , H01L2224/81193 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a through electrode with an insulation ring whose workability and functionality are both enhanced.SOLUTION: Independent insulation rings 62a and 62b are formed by filling an insulation substance into insulation ring annular grooves CGa and CGb formed through dry etching. Also, TSV side wall insulation rings 61a and 61b are formed by covering side walls of TSV through holes THa and THb formed through dry etching with insulation films. Further, a TSV 7 is formed by filling a dielectric, such as copper, into remaining parts of the TSV through holes THa and THb with seed/barrier layers 71 in-between. Thicknesses of the TSV side wall insulation rings 61 are around a half of widths of the insulation ring annular grooves CG, in other words, thicknesses of the independent insulation rings 62. As a result, it is possible to set the thicknesses of the TSV side wall insulation rings 61 at around a third of the thicknesses of the TSV side wall insulation rings in the case where the TSV side wall insulation rings are provided independently.
摘要翻译：要解决的问题：为通孔提供绝缘环，其可加工性和功能性都得到增强。解决方案：通过将绝缘物质填充到通过干蚀刻形成的绝缘环环形沟槽CGa和CGb中，形成独立的绝缘环62a和62b。此外，TSV侧壁绝缘环61a和61b通过用绝缘膜覆盖通过干蚀刻形成的孔THa和THb覆盖TSV的侧壁而形成。此外，通过在其间插入种子/阻挡层71的孔THa和THb将诸如铜的电介质填充到TSV的剩余部分中形成TSV 7。 TSV侧壁绝缘环61的厚度是绝缘环形环CG的宽度的大约一半，换句话说，是独立绝缘环62的厚度。结果，可以设定TSV侧的厚度在TSV侧壁绝缘环独立设置的情况下，TSV侧壁绝缘环的三分之一厚度的壁绝缘环61。版权所有（C）2013，JPO＆INPIT

50. 发明专利

JP2013114700A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013114700A
公开(公告)日：2013-06-10
申请号：JP2011257175
申请日：2011-11-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NOGUCHI HIDEKAZU
IPC分类号： G11C11/407
CPC分类号： G11C11/4094 , G11C7/00 , G11C8/06 , G11C8/08 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device by reducing the size of a selection circuit of a word line.SOLUTION: In the semiconductor device, a main word line is classified to a plurality of groups, and a main word driver selects the main word line according to address information. One group constituted by four main word lines MWL0 to MWL3 shares one level shifter 118. The address information includes a first address for group selection and a second address for main word line selection. The main word driver selects a first group selection circuit and a second group selection circuit 128a according to the first address, and the level shifter 118 of the selected second group selection circuit 128a outputs an action potential (low level). One main word line out of the plurality of main word lines MWL0 to MWL3 belonging to the selected second group selection circuit 128a is selected by the second addresses A3 and A4.
摘要翻译：要解决的问题：通过减小字线的选择电路的尺寸来减小半导体器件的尺寸。解决方案：在半导体器件中，主字线分为多个组，主字驱动器根据地址信息选择主字线。由四个主要字线MWL0至MWL3组成的一个组共享一个电平移位器118.地址信息包括用于组选择的第一地址和用于主字线选择的第二地址。主字驱动器根据第一地址选择第一组选择电路和第二组选择电路128a，并且所选择的第二组选择电路128a的电平移位器118输出动作电位（低电平）。属于所选择的第二组选择电路128a的多个主字线MWL0至MWL3中的一条主字线由第二地址A3和A4选择。版权所有（C）2013，JPO＆INPIT

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