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41. 发明专利

JP2007109826A Wiring board, semiconductor device, and its manufacturing method 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：JP2007109826A
公开(公告)日：2007-04-26
申请号：JP2005298186
申请日：2005-10-12
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： YAMAMICHI SHINTARO , KIKUCHI KATSU , KURITA YOICHIRO , SOEJIMA KOJI
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49816 , H01L21/6835 , H01L23/5383 , H01L23/5386 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2224/81801 , H01L2224/97 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01056 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01082 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a high connection reliability wiring board, a semiconductor device, and its manufacturing method, capable of connection of fine wirings and capable of high density connection among a plurality of semiconductor elements. SOLUTION: The semiconductor device comprises a flat-plate wiring board, a first LSI104 provided on one surface of the wiring board, sealing resin for covering the one surface and side surfaces of the first LSI104, and a second LSI204 provided on the other surface of the wiring board. The wiring board comprises conductive wiring 501 as a wiring layer, insulating resin as a support layer of the wiring layer, and a conductive through hole penetrating the wiring layer and the support layer. Lands 302 installed at a position which a peripheral end of the semiconductor element traverses, when viewed from a vertical upper portion of the interior of the land, among lands 301 including an external connection terminal are arranged as eccentrically located in their connection points with the wiring board formed on the same plane as the land. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够连接精细布线并且能够在多个半导体元件之间具有高密度连接的高连接可靠性布线板，半导体器件及其制造方法。解决方案：半导体器件包括平板布线板，设置在布线板的一个表面上的第一LSI104，用于覆盖第一LSI104的一个表面和侧表面的密封树脂和设置在第一LSI104上的第二LSI204 布线板的其他表面。布线板包括作为布线层的导电布线501，作为布线层的支撑层的绝缘树脂，以及穿透布线层和支撑层的导电孔。安装在半导体元件的外周端穿过的位置的陆地302被布置成偏心地位于与布线的连接点中的位置，当从陆地内部的垂直上部观察时，包括外部连接端子的陆部301 董事会与土地在同一架飞机上形成。版权所有（C）2007，JPO＆INPIT

42. 发明专利

JP2007096337A Wiring substrate for mounting semiconductor, semiconductor package, and its manufacturing method 审中-公开
标题翻译：用于安装半导体的接线基板，半导体封装及其制造方法
公开(公告)号：JP2007096337A
公开(公告)日：2007-04-12
申请号：JP2006313640
申请日：2006-11-20
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunction, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted with high density and high accuracy specifically on the both surfaces of a substrate, and which is excellent also in reliability, its manufacturing method, and a semiconductor package.
SOLUTION: A wiring substrate 5 for mounting semiconductor is a wiring substrate comprising at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 conducted by the wiring 2 and a via 3. The electrode pad 4 is prepared on the front and back surfaces of the insulating film 1 such that the front surface is exposed. At least a part of the side surface of the electrode pad is embedded in the insulating film 1. The insulating film 1 can be formed by forming the electrode pads 4 on two sheets of metal plates, laminating the insulating layer and the wiring on the electrode pad 4 and each metal plate, pasting the insulating layer together and unifying the layer, and removing the metal plate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体装置的布线基板，其有效用于半导体器件的高集成度，高速度或多功能的端子增加，以及端子之间的距离的窄间距，其中半导体器件可以特别地在基板的两个表面上高密度和高精度地安装，并且在可靠性，其制造方法和半导体封装中也是优异的。解决方案：用于安装半导体的布线基板5是至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3传导的多个电极焊盘4的布线基板。在绝缘膜1的前表面和后表面上制备电极焊盘4，使得前表面露出。电极焊盘的侧面的至少一部分嵌入在绝缘膜1中。绝缘膜1可以通过在两片金属板上形成电极焊盘4而形成，在电极上层压绝缘层和布线垫4和每个金属板，将绝缘层粘贴在一起并使层合并，并移除金属板。版权所有（C）2007，JPO＆INPIT

43. 发明专利

JP2006228919A Wiring board, semiconductor device, and their manufacturing method 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：JP2006228919A
公开(公告)日：2006-08-31
申请号：JP2005040062
申请日：2005-02-17
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , KURITA YOICHIRO , SOEJIMA KOJI
IPC分类号： H05K3/20 , H01L23/12 , H01L23/14
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2924/01322 , H01L2924/15192 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein a water system process is used to stably form a wiring structural body on a supporting substrate, and the wiring structural body can be easily peeled off from the supporting substrate. SOLUTION: The wiring board 10 includes a supporting substrate 11 and a wiring structural body 17 which is arranged on the supporting substrate 11 with an adhesion layer 24 in-between. The adhesion layer 24 is comprised of a first layer 12 made of a water-soluble material, and a second layer 13 which is formed so as to cover the entire surface of the first layer 12 and is made of a waterproof material. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种布线板，其中使用水系统工艺来在支撑基板上稳定地形成布线结构体，并且布线结构体可以容易地从支撑基板剥离。解决方案：布线板10包括支撑基板11和布置在支撑基板11上的布线结构体17，其间具有粘合层24。粘合层24由水溶性材料制成的第一层12和形成为覆盖第一层12的整个表面并由防水材料制成的第二层13构成。版权所有（C）2006，JPO＆NCIPI

44. 发明专利

JP2006032600A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006032600A
公开(公告)日：2006-02-02
申请号：JP2004208375
申请日：2004-07-15
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , HONDA KOICHI , SOEJIMA KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/12 , H01L23/52 , H01L27/04
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an enormous wiring structure to mitigate stress generated in a fine wiring structure, and operates at a large drive current and a high frequency with high reliability.
SOLUTION: A fine wiring structure 12 by laminating a first wiring layer and a first insulating layer alternately is provided on a semiconductor substrate 11, and a first enormous wiring structure 13a is provided by laminating a second wiring layer 15 having a thickness which is twice or more the first wiring layer and a second insulating layer 14, alternately. Further, a second enormous wiring structure 13b is provided on the first enormous wiring structure 13a by laminating a third wiring layer 17 having a thickness which is twice or more the first wiring layer and a third insulating layer 16 having an elastic modulus smaller than the second insulating layer 14 at 25 °C alternately. Thus, stress generated in the semiconductor device after being mounted to a mounting board is effectively mitigated in the first enormous wiring structure 13a and the second enormous wiring structure 13b, and stress applied to the fine wiring structure 12 can be reduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有巨大布线结构以减轻精细布线结构中产生的应力的半导体器件，并以高可靠性的大驱动电流和高频工作。解决方案：通过在半导体衬底11上设置层叠第一布线层和第一绝缘层的精细布线结构12，并且通过层叠具有厚度的第二布线层15来提供第一巨大布线结构13a 是第一布线层和第二绝缘层14的两倍以上。此外，通过层叠第一布线层的两倍以上的厚度的第三布线层17和弹性模量小于第二布线层的第三绝缘层16，在第一布线结构13a上设置第二大布线结构13b 绝缘层14交替地在25℃。因此，在第一巨大布线结构13a和第二巨大布线结构13b中，在安装到安装板上之后在半导体器件中产生的应力被有效地减轻，并且可以减小施加到精细布线结构12的应力。版权所有（C）2006，JPO＆NCIPI

45. 发明专利

JP2005039260A Stress relaxation structure and formation method therefor, stress relaxation sheet and manufacturing method therefor, and semiconductor device and electronic equipment 有权
标题翻译：应力松弛结构及其形成方法，应力松弛片及其制造方法及半导体器件及电子设备
公开(公告)号：JP2005039260A
公开(公告)日：2005-02-10
申请号：JP2004192446
申请日：2004-06-30
申请人： Nec Corp , 日本電気株式会社
发明人： MURAI HIDEYA , KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2924/15174
摘要： PROBLEM TO BE SOLVED: To provide a stress relaxation structure and its formation method that is superior in stress relaxation effects upon thermal stress and improves the reliability of a semiconductor device, and to provide a stress relaxation sheet and its manufacturing method, and a semiconductor device, having the stress relaxation sheet and electronic equipment having the semiconductor device. SOLUTION: The stress relaxation structure, which has a wave-shaped insulating layer 4 that exists between a chip 5, on which a semiconductor device 6 is formed and a mounting substrate 7, has the above problem resolved by making the wiring 3 wave-shaped. In addition, the stress relaxed structure is formed, by forming an insulating layer 4 having a wavy shape that displaces in the thickness direction on a process substrate or a wafer, having a semiconductor element and forming wiring 3 having a wavy shape on the insulating layer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种应力松弛结构及其在热应力下的应力松弛效果优异的形成方法，提高半导体装置的可靠性，提供应力松弛片及其制造方法，具有应力松弛片的半导体器件和具有半导体器件的电子设备。解决方案：在其上形成有半导体器件6的芯片5和安装基板7之间存在波形绝缘层4的应力松弛结构通过使布线3解决了上述问题波浪形。此外，通过在具有半导体元件的工艺衬底或晶片上形成具有在厚度方向上移位的波浪形状的绝缘层4，并且在绝缘层上形成具有波状的布线3，形成应力松弛结构。版权所有（C）2005，JPO＆NCIPI

46. 发明专利

JP2004179647A Wiring board, semiconductor package, and method for producing base insulating film and wiring board 有权
公开(公告)号：JP2004179647A
公开(公告)日：2004-06-24
申请号：JP2003382418
申请日：2003-11-12
申请人： Nec Corp , 日本電気株式会社
发明人： ORITO NAONORI , HONDA KOICHI , HO KEIICHIRO , MURAI HIDEYA , KIKUCHI KATSU , BABA KAZUHIRO
IPC分类号： H05K3/46 , H01L21/60 , H01L23/12
CPC分类号： H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011
摘要： PROBLEM TO BE SOLVED: To provide a wiring board, in which various devices such as semiconductor device is mounted densely, a high-speed interconnection and dense fine-wiring are easily formed, and reliability is high; a semiconductor package using the wiring board; and to provide a method for producing the wiring board. SOLUTION: A base insulating film 7 is provided on a circuit board 13. In the base insulating film 7, it is set so that the thickness is 3 to 100 μm, breakdown strength is 80 MPa or larger at 23°C, and the elasticity modulus is 2.3 GPa or larger at 150°C. Assuming that the breakdown strength is a (MPa) at -65°C, and the breakdown strength is b (MPa) at 150°C, the ratio: a/b is set to 2.5 or smaller. Assuming that the elasticity modulus is c (GPa) at -65°C, and the elasticity modulus is d (GPa) at 150°C, the breakdown strength a, b and the elasticity modulus c, d satisfy the formula. COPYRIGHT: (C)2004,JPO

47. 发明专利

JP2006351963A WIRING BOARD AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2006351963A
公开(公告)日：2006-12-28
申请号：JP2005178452
申请日：2005-06-17
申请人： NEC CORP , NEC ELECTRONICS CORP
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , MAEDA TAKEHIKO , HONDA KOICHI , OGAWA KENTA , TSUKANO JUN
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein the cross-sectional shape of each of vias adopts a shape comprising parts of similar figures overlapped with each other so as to reduce hindrance to high density processing, to effectively increase the cross sectional area of the vias, and to prevent increase in the wiring resistance thereby realizing stable operations of semiconductor elements and to provide a manufacturing method thereof. SOLUTION: The wiring board on which the semiconductor elements or electronic components are mounted includes a plurality of wiring layers 11, 13, insulating layers 12 each provided between the wiring layers 11, 13, and the vias 16 provided to the insulation layers 12 to electrically connect the wiring layers 11, 13. In this wiring board, the cross-sectional shape of each via 16 shown on a plane in parallel with the wiring layers 11, 13 indicates the similar figures (circles) parts of which are overlapped. COPYRIGHT: (C)2007,JPO&INPIT

48. 发明专利

JP2004006989A METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2004006989A
公开(公告)日：2004-01-08
申请号：JP2003299304
申请日：2003-08-22
申请人： NEC CORP
发明人： KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO , MATSUI KOJI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a new semiconductor package substrate which is quipped with a large number of pins, easily improved in density, micronized, superior in reliability, and not required to be equipped with a stiffener by reforming a conventional semiconductor package substrate and improving a multilayer wiring structure film in evenness and to provide a method of manufcturing a semiconductor device using the new semiconducctor package substrate. SOLUTION: The multilayer wiring structure film 15 is laminated on a metal base 11 of a metal plate having an opening in which a semiconductor device 16 is fitted, the semiconductor device 16 is fitted into the opening formed in the metal base 11 and connected to a metal pad 12 in a flip-chip mounting manner. Furthermore, solder balls 19 for BGA are mounted on a metal pad 29. At this time, the surface of the semiconductor device 16 is arranged on the same plane with the that of the metal base 11. COPYRIGHT: (C)2004,JPO

49. 发明专利

JP2003243833A MULTILAYER WIRING STRUCTURE 审中-公开
公开(公告)号：JP2003243833A
公开(公告)日：2003-08-29
申请号：JP2002040347
申请日：2002-02-18
申请人： NEC CORP
发明人： KIKUCHI KATSU , ORITO NAONORI
IPC分类号： H05K1/11 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring structure having a high via hole connection reliability. SOLUTION: The multilayer wiring structure has a lower layer conductor wiring 12 and an upper layer conductor wiring 14 insulated from each other by an interlayer insulation film 13 provided with a via hole 15 for electrically conducting two conductor wiring layers. The via hole has a lower end opening above both the lower layer conductor wiring and an insulator mounting it, and the upper layer conductor wiring is connected with the lower layer conductor wiring 12 through the insulator 11 exposed into the opening at the lower end of the via hole. The interlayer insulation film 13 has material characteristics selected for the insulator such that the lower end on the surface of the interlayer insulation film constituting the circumferential surface of the via hole touches the insulator at a contact angle not larger than a specified value. The specified contact angle is 90°, the insulator is composed of organic resin and the aspect ratio of the via hole can be set not lower than 0.5 when the interlayer insulation film is composed of fluorene resin. COPYRIGHT: (C)2003,JPO

50. 发明专利

JP2004006990A SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2004006990A
公开(公告)日：2004-01-08
申请号：JP2003299312
申请日：2003-08-22
申请人： NEC CORP
发明人： KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO , MATSUI KOJI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a new semiconductor package substrate which is quipped with a large number of pins, easily improved in density, miniaturized, superior in reliability, and not required to be equipped with a stiffener by reforming a conventional semiconductor package substrate and improving a multilayer wiring structure film in evenness and to provide a semiconductor device using the new semiconductor package substrate. SOLUTION: The multilayer wiring structure film 15 is laminated on a metal base 11 of a metal plate having an opening in which a semiconductor device 16 is fitted, the semiconductor device 16 is fitted into the opening formed in the metal base 11 and connected to a metal pad 12 in a flip-chip mounting manner. Furthermore, solder balls 19 for BGA are mounted on a metal pad 29. At this point, the surface of the semiconductor device 16 is arranged on the same plane with the that of the metal base 11. COPYRIGHT: (C)2004,JPO

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