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41. 发明专利

JPS59114993A Digital exchange system 失效
标题翻译：数字交换系统
公开(公告)号：JPS59114993A
公开(公告)日：1984-07-03
申请号：JP22444482
申请日：1982-12-21
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , NAITOU SHIYUNICHI , MAKIYAMA TAKAO
IPC分类号： H04Q11/04
CPC分类号： H04Q11/04
摘要： PURPOSE:To facilitate the bus setting control by dividing the medium/high- speed data of the input side to perform the exchange processing with the bus setting corresponding to the number of data divisions and reading out the divided data from the frame number information given from a frame counter at the output side to reproduce the data. CONSTITUTION:When the data of N times as much as 64Kb/s is supplied to a medium/high-speed data trunk DT1, the medium/high-speed data is divided by a data distributing circuit DDB. A data restoring circuit DCB of a trunk DT2 at the output side contains a buffer memory corresponding to the bus to store temporarily the divided data passed through each bus of a time division network TDSW. Then the divided data of frame number information coincident with the frame number information given from a frame counter FCTR2 are read out, and the medium/high-speed data is reproduced. In such a way, the medium/high-speed data can be reproduced in a correct order despite different delay times of buses of the network TDSW.
摘要翻译：目的：为了通过划分输入侧的介质/高速数据来实现总线设置控制，使用与数据分割数相对应的总线设置进行交换处理，并从从输出侧的帧计数器来再现数据。构成：当将N倍高达64Kb / s的数据提供给中/高速数据中继线DT1时，中/高速数据被数据分配电路DDB分频。输出侧的中继线DT2的数据恢复电路DCB包含与总线相对应的缓冲存储器，用于临时存储经过时分网络TDSW的各个总线的划分数据。然后，读出与从帧计数器FCTR2给出的帧号信息一致的帧号信息的划分数据，再生中高速数据。以这种方式，即使网络TDSW的总线的延迟时间不同，也可以以正确的顺序再现中/高速数据。

42. 发明专利

JPS5854716B2 失效
公开(公告)号：JPS5854716B2
公开(公告)日：1983-12-06
申请号：JP13799179
申请日：1979-10-25
申请人： FUJITSU LTD
发明人： SUTANI YOSHIAKI , MINAMITANI EIJI , SUNOCHI TATSUO
IPC分类号： H04Q11/04

43. 发明专利

JPS5857887A INITIAL INHIBITION SYSTEM FOR MEMORY READOUT SIGNAL 失效
公开(公告)号：JPS5857887A
公开(公告)日：1983-04-06
申请号：JP15552881
申请日：1981-09-30
申请人： FUJITSU LTD
发明人： OZAWA YUKIO , KOUNO HISAO , SUTANI YOSHIAKI
IPC分类号： H04Q3/54 , H04Q3/545 , H04Q11/04
摘要： PURPOSE:To normally start the exchange operation, by stopping the readout output of a line control memory, until the content of the memory is entirely newly rewritten, at starting after a power failure. CONSTITUTION:At the application of power supply, when a power supply VCC of a control section CP is risen, in an FF of a start means ST, a data terminal D goes to 1 at first and a clock terminal C goes to 1 with a delay. Thus, the FF is set to 1 to inhibit a gate AG. Further, an electronic exchange starts the operation through the application of power supply, the state of line from a scanning section (not shown) is processed at a main controller and control information is applied to a signal control section SPR, which forms a line control signal SD to all the lines and writes the signal to a line control memory SDM together with the write address corresponding to the lines. When the write of all the lines is finished, the SPR resets the FF to turn on the gate AG. The line control signal in the SDM is cyclily sequentially read out to control a line corresponding section SP.

44. 发明专利

JPS5775054A Testing system for digital coference telephone connection device 失效
标题翻译：数字电话电话连接设备测试系统
公开(公告)号：JPS5775054A
公开(公告)日：1982-05-11
申请号：JP10397880
申请日：1980-07-29
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , SHIRAI HITOSHI , MASUDA TOORU
IPC分类号： H04M3/26 , H04M3/56
CPC分类号： H04M3/561
摘要： PURPOSE:To test always a conference telephone connection device even during operating of this device, by provoding a fixed data input device and a device, which detects dissidence between the operation result and an expected value, in the conference telephone connection device. CONSTITUTION:A testing device TST is provided in a conference telephone connection device CFC, and this device TST is provided with a fixed data input device FXD and a dissidence detecting device DET. On PCM signal highways (a) and (b), fixed data is inputted from the fixed data input device FXD to a time slot which is not used for the digital conference telephone on these highways; and the result of the digital multiple operation processing in the conference telephone connection device CFC is compared with a expected value and dissidence between them is detected by the dissidence detecting device DET. If the dissidence is detected, a fault occurs in the conference telephone connection device CFC.
摘要翻译：目的：在会议电话连接装置中，即使在操作本装置的过程中，即使在该装置的操作过程中，也可以通过编码固定的数据输入装置和装置来检测运算结果与预期值之间的异常，即时测试会议电话连接装置。构成：在会议电话连接装置CFC中提供测试装置TST，并且该装置TST具有固定数据输入装置FXD和不一致检测装置DET。在PCM信号高速公路（a）和（b）上，固定数据从固定数据输入装置FXD输入到在这些高速公路上不用于数字会议电话的时隙; 将会议电话连接装置CFC中的数字多重操作处理的结果与预期值进行比较，并且通过不一致检测装置DET检测它们之间的不一致。如果检测到异议，会议电话连接设备CFC发生故障。

45. 发明专利

JPS5730489A Time-division memory system 失效
标题翻译：时分存储系统
公开(公告)号：JPS5730489A
公开(公告)日：1982-02-18
申请号：JP10433680
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , KOUNO HISAO
IPC分类号： H04Q3/52 , H04Q11/04
CPC分类号： H04Q11/04
摘要： PURPOSE:To decrease the number of memories, and to simplify the control over transmission and reception which reducing the price of a channel device, by using part of a channel memory, included in the time-division switch of a digital switchboard, for no-channel data. CONSTITUTION:Data transferred from a multiplexer 2 in a circuit correspondence part 1 to a highway 4, having 15-frame multiframe constitution by assigning 120 channels of channel signals and 8 channels of no-channel signals to one frame, are transmitted over 120 channels each of the channel and no-channel signals. Each memory cycle of the channel memory 9 of a time-division switch 8 consists of four steps of sequential writing, random reading, no-channel data reading, and random reading. According to outputs of counters 11 and 21, data are written by being specified by an address selector and channel data read out by the address RRA of a holding memory are transferred to the next stage via a register 23. No-channel data are readout by a signal controller 14 and transferred to the device 14.
摘要翻译：目的：为了减少存储器的数量，并且通过使用包括在数字总机的时分开关中的部分通道存储器来简化对传输和接收的控制，从而降低了通道设备的价格，频道数据构成：从电路对应部分1中的多路复用器2传送到高速公路4的数据，通过将120个信道信号和无信道信号的8个信道分配给一个帧，具有15帧复帧结构，每个信道在120个信道上传送的通道和无通道信号。时分开关8的通道存储器9的每个存储周期由顺序写入，随机读取，无通道数据读取和随机读取的四个步骤组成。根据计数器11和21的输出，通过由地址选择器指定数据并且由保持存储器的地址RRA读出的通道数据经由寄存器23被传送到下一级。无通道数据由信号控制器14并传送到设备14。

46. 发明专利

JPS5728491A Channel control system 失效
标题翻译：通道控制系统
公开(公告)号：JPS5728491A
公开(公告)日：1982-02-16
申请号：JP10345380
申请日：1980-07-28
申请人： Fujitsu Ltd
发明人： SUTANI YOSHIAKI , KOUNO HISAO , ASHIHARA SHIYUUICHI
IPC分类号： H04Q3/545 , H04Q11/04
CPC分类号： H04Q11/04
摘要： PURPOSE:To increase the usage efficiency of highway, by using a channel memory consisting of separate regions for audio and signal. CONSTITUTION:Incoming and outgoing channel memories SPMF' and SPMB' in a switch module SM' are formed with audio region TSM and signal region NTM, respectively. A multiplex signal from multiplex lines HW-1 and HW-2 is further multiplexed and controlled at a control memory CTLM, and audio and control signals are separately stored at the corresponding location of TSM or NTM channel. The CTLM can indicate whether the channel of the HW-1 and HW-2 is audio or control signal in every channel. Thus, the line corresponding section LM-2' accommodating a PCM line can multiplex 128 lines as they are to all the channels of the HW-2'. As well known, the LM-1' multiplexes subscribers SUB of 120 on the HW-1 with the 8 control channels.
摘要翻译：目的：提高高速公路的使用效率，通过使用由独立的音频和信号区域组成的通道存储器。构成：开关模块SM'中的输入和输出通道存储器SPMF'和SPMB'分别形成有音频区域TSM和信号区域NTM。来自多路复用线路HW-1和HW-2的多路复用信号被进一步复用并控制在控制存储器CTLM处，音频和控制信号分别存储在TSM或NTM信道的对应位置处。 CTLM可以指示HW-1和HW-2的通道是每个通道中的音频还是控制信号。因此，容纳PCM线路的线路对应部分LM-2'可以将128条线路原样复用到HW-2'的所有信道。众所周知，LM-1将HW-1上的120个用户SUB与8个控制信道进行多路复用。

47. 发明专利

JPS5648749A ANNOUNCEMENT CONTROL SYSTEM OF TELEPHONE EXCHANGE SYSTEM 失效
公开(公告)号：JPS5648749A
公开(公告)日：1981-05-02
申请号：JP12423279
申请日：1979-09-28
申请人： FUJITSU LTD
发明人： TABU TAKASHI , SAITOU HIROSHI , SUTANI YOSHIAKI
IPC分类号： H04M3/50 , H04Q3/555 , H04Q3/58
摘要： PURPOSE:To attain accurate announcement while improving the efficiency of utilization of a transmission system channel, by providing a master station with an announcement source and by sending announcement to a subscriber by changing a circuit-testing leading-in circuit over to an announcement-repeating circuit coordinate part. CONSTITUTION:When the telephone exchange system is busy, announcement is sent to a subscriber with the receiver hooked off. In this case, circuit test leading-in circuits 31-3N are connected to announcement sound source 72 and announcement repeating circuit coordinate part 73 via circuit testing device 71 under the command of common control circuit 52 in master station 1. Simultaneously, one channel of the transmission line is assigned for announcement under the command of circuit 52. At remote station 10, switch 91 is controlled under the command of common control circuit 502 to made circuit connections with circuit test leading-in circuits 201-20N and announcement from sound source 72 in master station 1 is sent out to subscribers 801-80N. The announcement sound from sound source 72 is also sent out to subscribers 81-8N of master station 1. Test leading-in wires are used for announcement in common and the sound source is provided at only the master station, so that the utilization efficiency of the transmission system channel can be improved.

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