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41. 发明专利

JPS60186134A TESTING DEVICE FOR SATELLITE COMMUNICATION 失效
公开(公告)号：JPS60186134A
公开(公告)日：1985-09-21
申请号：JP4159384
申请日：1984-03-05
申请人： FUJITSU LTD
发明人： SATOU HIROAKI
IPC分类号： H04B7/15 , H04B17/40
摘要： PURPOSE:To integrate and economize testing means for a master station and plural slave station and to conduct a test nearly in a practical use state by providing a single integrated testing device for a master station device and plural slave station devices which constitute a satellite communication system. CONSTITUTION:The single integrated testing device TSTE is provided to the master station device CS and plural slave station devices SS. The device TSTE is equipped with a test switch TSW, signal processor SP, delay generating circuit DJG, main storage device MM, and input/output controller IOC and is connected to a display device DPY and a keyboard KB through IOC. When the confrontation between devices CS and SS or devices SS is tested, a specific command is inputted to KB and then TSW makes a connection between objective CS and SS, or SS and SS. Then, a control signal and a speech signal between respective devices are transmitted and received to confirm the total function between the devices. Further, when TSW is so operated as to insert a circuit DJG, the control signal and speech signal are given long delay time and delay jitters characteristic to satellite communication, and the test is carried out nearly in the practical use state.

42. 发明专利

JPS59134955A Signal supervisory system 失效
标题翻译：信号监控系统
公开(公告)号：JPS59134955A
公开(公告)日：1984-08-02
申请号：JP953683
申请日：1983-01-24
申请人： Fujitsu Ltd
发明人： SATOU HIROAKI
IPC分类号： H04M3/22 , H04Q11/04
CPC分类号： H04M3/303
摘要： PURPOSE:To supervise easily a digitized signal transmitted on a subscriber line by branching and selecting a signal transmitted via the subscriber line and inputting the signal to a subscriber line accommodating terminal of an exchange. CONSTITUTION:A branching circuit 9 branches a signal (s) transmitted via a corresponding subscriber line 2 and transmits it to a selecting circuit 10. The selecting circuit 10 selects one of branching circuits based on a command of a signal controller 50 and inputs the signal (s) transmitted from the branching circuit 9 to a subscriber line accommodating terminal of a line concentrator 4 as communication information (c). A channel used as a supervisory path (m) is set between the subscriber line accommodating terminal and a signal supervisory device 80 and the signal (s) inputted by the selecting circuit 10 is transmitted to the signal supervisory device 80. Thus, a command is inputted to the signal controller 50 via a controller 6 and the signal (s) transmitted via a subscriber line 2 is transmitted automatically to the signal supervisory device 80 by making the selecting circuit 10 select the branching circuit 9 corresponding to the subscriber line 2 being the objective of supervision.
摘要翻译：目的：通过分支和选择通过用户线传输的信号并将信号输入到交换机的终端的用户线，来容易地监视在用户线路上传输的数字化信号。分支：分支电路9分支经由相应的用户线路2发送的信号，并将其发送到选择电路10.选择电路10基于信号控制器50的命令选择一个分支电路，并输入信号作为通信信息（c）从分支电路9发送到线路集中器4的用户线容纳终端。在用户线容纳终端和信号监控装置80之间设置用作监控路径（m）的信道，并且将由选择电路10输入的信号发送到信号监控装置80.因此，命令是经由控制器6输入到信号控制器50，并且经由用户线路2发送的信号通过使选择电路10选择与用户线路2相对应的分支电路9自动发送到信号监控装置80 监督目标。

43. 发明专利

JPS59131254A Fault detecting system 失效
标题翻译：故障检测系统
公开(公告)号：JPS59131254A
公开(公告)日：1984-07-28
申请号：JP561483
申请日：1983-01-17
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： SATOU HIROAKI , KOGURE KOUJI , HIRAHARA HIDEO , OGUCHI SEISHIROU , KATAYAMA TADASHI
IPC分类号： H04M3/22 , H04M3/24 , H04Q1/20 , H04Q3/60
CPC分类号： H04M3/244
摘要： PURPOSE:To decide quickly a faulty line concentration multiplex part producing a fault by an overall decision obtained from the result of both collation test and signal return test. CONSTITUTION:The test digital signal is sent back to line concentration multiplex parts CSW0 and CSW1 via a return circuit RP and then sent to a selecting circuit SEL2 via channels P1 and P2. Then only the test digital signal sent from the using line concentration multiplex part CSW0 is selected and sent back to a distribution stage channel network DSW. A test circuit TST compares the sent- back test digital signal with the transmitted original digital signal. When the coincidence is obtained from the comparison, it is decided that the circuit RP is normal. While a fault is decided if no coincidence is obtained. Therefore a fault is discriminated between the parts CSW0 and CSW1 based on the result of the signal return test if a collating circuit M1 or M2 detects no coincidence from the above-mentioned comparison.
摘要翻译：目的：通过从整理测试和信号返回测试的结果获得的总体决策，快速确定故障线路集中复用部分产生故障。结论：测试数字信号通过返回电路RP发送回线路集中复用部分CSW0和CSW1，然后通过信道P1和P2发送到选择电路SEL2。然后只有从使用线路集中复用部分CSW0发送的测试数字信号被选择并发回到分配级信道网络DSW。测试电路TST将发送的测试数字信号与发送的原始数字信号进行比较。当从比较获得一致时，判定电路RP是正常的。虽然如果没有获得巧合就决定了故障。因此，如果对照电路M1或M2检测到与上述比较不一致，则基于信号返回测试的结果，在部件CSW0和CSW1之间鉴别故障。

44. 发明专利

JPS55133432A METAL PLATING OF PLASTIC PRINTING TYPE 失效
公开(公告)号：JPS55133432A
公开(公告)日：1980-10-17
申请号：JP4104979
申请日：1979-04-06
申请人： FUJITSU LTD
发明人： WADA HIROSHI , SATOU HIROAKI , SUSAO HITEMITSU
IPC分类号： C23C18/16 , C08J7/04 , C23C18/40 , C23C28/00
摘要： PURPOSE:To manufacture a metal-plated plastic printing type having high hardness as well as high impact strength, and resistant to cracking of the metallic layer, by depositing a copper layer to the surface of a molded plastic printing type by electrolytic plating, and forming a reinforcing metallic layer on the copper layer by semigloss nickel plating. CONSTITUTION:For example, a type wheel 1 composed of a boss 2, a type base 3 and printing types 4 is integrally molded with acetal resin, etc. The surface of the type 4 is roughened by mechanical etching, and plated with a copper layer of 5-10 microns thick by the successive electroless plating and electrolytic plating. The surface of the copper layer is plated with a reinforcing metallic layer by semigloss nickel plating.

45. 发明专利

JPS5335308A CALL DISTRIBUTION SYSTEM 失效
公开(公告)号：JPS5335308A
公开(公告)日：1978-04-01
申请号：JP11050376
申请日：1976-09-13
申请人： FUJITSU LTD
发明人： SOGA KENTAROU , HATANO TOSHIICHIROU , OGAWA TOORU , TAKANO MASAAKI , SATOU HIROAKI
IPC分类号： G06F15/16 , G06F15/177 , H04Q3/545
摘要： PURPOSE:To unify the process load between CPUs and to inhibit an input to the assigned CPU when a fault occurs in the CPU. Thus, the process load can be unified between other CPUs.

46. 发明专利

JPS60173993A MULTIPLE ADDRESS COMMUNICATION CHANNEL DEVICE 失效
公开(公告)号：JPS60173993A
公开(公告)日：1985-09-07
申请号：JP2975084
申请日：1984-02-20
申请人： FUJITSU LTD
发明人： SATOU HIROAKI
IPC分类号： H04Q11/04
摘要： PURPOSE:To enable collection of digital information without using a dedicated trunk by extracting information from a channel memory to send it to a communication line and deleting information to be stored in an address corresponding to a transferring line. CONSTITUTION:An address in correspondence to a receiving line of a channel memory SPM is stored in an address in correspondence to a receiving line of a channel controlling memory CM. At the arrival of information from the receiving line, the device extracts information stored in the transferring line corresponding address of the memory SPM, takes information arriving from the receiving line and AND, and stores them in said SPM address. When a transferring line corresponding address is supplied from a counter circuit CNT, the device extracts information from the memory SPM and sends to the communication line, and information stored in the transferring line corresponding address is deleted by a deletion pattern of a deletion pattern generating circuit PG.

47. 发明专利

JPS59134935A Multiplex receiving circuit of serial code 失效
标题翻译：串行码多路复用接收电路
公开(公告)号：JPS59134935A
公开(公告)日：1984-08-02
申请号：JP953083
申请日：1983-01-24
申请人： Fujitsu Ltd
发明人： KITAMURA NOBUAKI , SATOU HIROAKI
IPC分类号： H03M9/00 , H04J3/00 , H04J3/02 , H04J3/04 , H04L5/22
CPC分类号： H04J3/00
摘要： PURPOSE:To realize economically a circuit to be controlled simply by receiving a partial code, revising a stored content of the 1st address of a storage section by the partial code, storing the code revised by the partial code transmitted at the last frame to the 2nd address and outputting a code completed at the 2nd address in parallel. CONSTITUTION:When a code bit Cmk of the m-th line arrives, a storage content of an address (m) is read by a write data editing circuit 8 and after it is revised by the Cmk, it is stored in the address (m) sttended with a write signal (w) from a control circuit 13. Thus, the code from the address 0 to the address 127 in a memory 7 is all revised. Then, in a readout time area from a time slot TS0 to TS127 in a frame F7, the circuit 8 completes a new code by revising the 7-th bit D7 of the stored content by arriving code bits C07-C1277. The most significant bit a7 of the address applied via a gate 12 is set to a logical value 1. Thus, the circuit 8 stores the completed code to addresses 128-255(completed code storaging area 72) of the memory 7.
摘要翻译：目的：为了简单地通过接收部分代码来经济地实现要控制的电路，通过部分代码修改存储部分的第一地址的存储内容，将由最后一帧发送的部分代码修改的代码存储到第二个地址并输出在第二地址并行完成的代码。构成：当第m行的代码位Cmk到达时，地址（m）的存储内容由写入数据编辑电路8读取，并且在被Cmk修改之后，存储在地址（m）中）与来自控制电路13的写入信号（w）相对应。因此，存储器7中的地址0到地址127的代码都被修改。然后，在帧F7中从时隙TS0到TS127的读出时间区域中，电路8通过到达码位C07-C1277修改存储的内容的第7位D7来完成新的代码。经由门12施加的地址的最高有效位a7被设置为逻辑值1.因此，电路8将完成的代码存储到存储器7的地址128-255（完成代码存储区域72）。

48. 发明专利

JPS59114925A Detecting circuit of input and output fault 失效
标题翻译：检测输入和输出故障电路
公开(公告)号：JPS59114925A
公开(公告)日：1984-07-03
申请号：JP22461482
申请日：1982-12-20
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： SHINOZUKA TAKASHI , SANBE TAKESHI , GOUHARA SHINOBU , MUKAI KAZUHIKO , SATOU HIROAKI
IPC分类号： H03L7/095
CPC分类号： H03L7/095
摘要： PURPOSE:To constitute the titled circuit by logic elements and to miniaturize the circuit by providing a differentiating circuit which differentiates the changing point of the input signal of a phase locked oscillation circuit to obtain the 1st output and then differentiates the output signal of said oscillation circuit to obtain the 2nd output, respectively, and detecting the coincidence and discordance between the 1st and 2nd outputs. CONSTITUTION:A phase locked oscillation circuit PLO1 is provided with a phase comparator 2, loop filter 3 and a voltage controlled oscillator 4. An input signal IN is applied to the comparator 2 and to a differentiating circuit 16. The changing point of the signal IN is differentiated by a delay circuit 21 and an AND circuit 22 to deliver the 1st signal (e). While the changing point of the output signal of the osillator 4 is differentiated by a delay circuit 23 and an AND circuit 24 of the circuit 16 to deliver the 2nd signal (f). The coincidence and dissidence between the signals (e) and (f) are detected by an asynchronism detecting circuit 5. Then an asynchronism detecting output (b) is outputted when no coincidence is detected between both signals, and only logic elements are used to constitute a circuit for miniaturization.
摘要翻译：目的：通过逻辑元件构成标题电路，并通过提供一个微分电路来区分电路的小电路，该差分电路区分锁相振荡电路的输入信号的变化点以获得第一输出，然后区分所述振荡电路的输出信号分别获得第二输出，并检测第一和第二输出之间的一致性和不一致性。构成：锁相振荡电路PLO1具有相位比较器2，环路滤波器3和压控振荡器4.输入信号IN被施加到比较器2和微分电路16.信号IN的变化点由延迟电路21和“与”电路22进行区分，以传送第一信号（e）。虽然振荡器4的输出信号的变化点被电路16的延迟电路23和与电路24区分，以输送第二信号（f）。信号（e）和（f）之间的一致性和不一致性由异步检测电路5检测。然后，当在两个信号之间没有检测到符合时，输出异步检测输出（b），并且仅使用逻辑元件构成用于小型化的电路。

49. 发明专利

JPS5979667A Method for detecting fault of time division highway 失效
标题翻译：检测时间段高速公路故障的方法
公开(公告)号：JPS5979667A
公开(公告)日：1984-05-08
申请号：JP18918782
申请日：1982-10-29
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： SHIMIZU TAKEHIKO , SANBE TAKESHI , KAMEDA HARUTOSHI , HARIMOTO KOUICHI , SATOU HIROAKI
IPC分类号： H04M3/26 , H04M3/22 , H04M3/24
CPC分类号： H04M3/244
摘要： PURPOSE:To detect a fault by the small number of hardwares by connecting a frame synchronization supervising circuit to plural highways in common and by leading signals received from the time division highways successively to the frame synchronization supervising circuit. CONSTITUTION:The frame synchronization supervising circuit DET is connected to plural highways in common and selecting circuits SEL lead clocks C and frames F of respective highways to the supervising circuit successively. The selecting circuits SEC, a distributing circuit DEC, and the supervising circuit DET operate at the timing of a timing circuit TIM. The supervising time of respective highways is sufficient for discriminating a fixed fault such as the disconnection of the highway from an intermittent fault such as noise. Fault information ERR outputted from the supervising circuit DET is sent to holding memories FF which are supervised by the distributing circuit DEC and are set up in accordance with respective highways.
摘要翻译：目的：通过将帧同步监控电路连接到多个高速公路，并将时分高速公路接收的前导信号连续连接到帧同步监控电路，来检测少量硬件的故障。构成：帧同步监视电路DET连接到多个公共高速公路，并且连续地将各个高速公路的各个高速公路的SEL引导时钟C和帧F选择到监视电路。选择电路SEC，分配电路DEC以及监控电路DET在定时电路TIM的定时工作。各高速公路的监控时间足以区分高速公路断线等固定故障，例如噪声等间歇性故障。从监控电路DET输出的故障信息ERR被发送到由分配电路DEC监控的保持存储器FF，并且根据相应的高速公路设置。

50. 发明专利

JPS57134590A PARTIAL PLATING METHOD 失效
公开(公告)号：JPS57134590A
公开(公告)日：1982-08-19
申请号：JP1945781
申请日：1981-02-12
申请人： FUJITSU LTD
发明人： IMAOKA JIYUUTAROU , KOJIMA KIYOSHI , SATOU HIROAKI , SUSAO HITEMITSU
IPC分类号： C25D5/02
摘要： PURPOSE:To prevent the entry of a treating soln. into a non-plating region part and to perform partial plating at a low cost by immersing only the plating region of an object to be plated covered with the non-plating region into the plating soln. thereby plating the same. CONSTITUTION:A motor 8 is coupled via a shaft 7 fitted with a plating article 5 above a plating soln. cell 1, and an electric power source E is connected to the other. A jig disposing a cathode 4 togehter with the motor 8 is provided to the shaft 7, and the article 5 having covers 6, 6 is fitted and set to the shaft 7 by means of said jig. Next, only the plating region part of the article 5 is immersed in a plating soln. 2, and the shaft 7 is rotated in an arrow direction by the revolution of the motor 8. As a result, the article 5 fitted to the shaft 7 is rotated at the same time, and during this time, the part requiring plating is plated. At this time, the entry of the soln. 2 into the part requiring no plating in the non- plating region is prevented by centrifugal force of revolution. It is also possible to accomplish this by a method of using anode 3 in order to improve the convection of the treating soln. for higher efficiency of the plating treatment.

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