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    • 31. 发明专利
    • LOCK DETECTING CIRCUIT
    • JPH04208704A
    • 1992-07-30
    • JP40006990
    • 1990-12-01
    • SANYO ELECTRIC CO
    • MEYA MASATO
    • H04S7/00H03G3/02H03G3/10H04H1/00H04H40/36
    • PURPOSE:To prevent the malfunction due to noise by discriminating whether the state is changed plural times within a certain time or not to detect the lock state of an up/down counter. CONSTITUTION:The state change of the output signal of a direction data generating circuit 27 synchronized with a clock signal is detected by a state change detecting circuit 29. If the state change sporadically occurs by the malfunction of the up/down counter due to noise, the state change is intermittently counted by a counting circuit 30 at intervals, and the time is required till the occurrence of a count completion signal. Therefore, a timing signal is generated from a timing set signal 32 kept in the waiting state to reset the counting circuit 30 and an RS-FF 31. As the result, a gate circuit 33 goes to the cut-off state and the counting circuit 30 is cleared, and therefore, the lock state is not discriminated and the circuit is returned to the initial state.
    • 38. 发明专利
    • AM/FM STEREO RECEIVER AND AM STEREO/FM STEREO RECEIVER
    • JPH03226020A
    • 1991-10-07
    • JP2008290
    • 1990-01-30
    • SONY CORP
    • YAMAZAKI DAISUKE
    • H04B1/16H04H1/00H04H40/36H04H40/45
    • PURPOSE:To decrease the circuit scale by controlling an oscillating frequency of a variable oscillator based on a phase comparison output from an FM orthogonal synchronizing detector at the reception of an FM broadcast and based on a phase comparison output from an AM orthogonal synchronizing detector at the reception of an AM broadcast. CONSTITUTION:An AM orthogonal synchronizing detector 4 acts like a phase comparator and constitutes an AM PLL circuit 17 together with a low pass filter 5 of a PLL circuit 19, a voltage controlled oscillator 6 and a 1/8 frequency divider 7 of a frequency division circuit 16. Moreover, an FM orthogonal synchronizing detector 11 acts like a phase comparator and constitutes an FM PLL circuit 18 together with the voltage controlled oscillator 6, 1/8, 1/6, 1/4 frequency dividers 7, 12, 13 of the frequency division circuit 16 and a low pass filter 5. Since the voltage controlled oscillator 6, the 1/8 frequency divider 7 and the low pass filter 5 of the PLL circuit 19 are used in common in this way, the circuit scale is made small regardless of the integration of the AM (AM stereo) receiver and the FM stereo receiver.