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31. 发明专利

JPS59149054A Planar type transistor 失效
标题翻译：平面型晶体管
公开(公告)号：JPS59149054A
公开(公告)日：1984-08-25
申请号：JP2336283
申请日：1983-02-15
申请人： Matsushita Electric Works Ltd
发明人： ABE TOSHIROU
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain high dielectric-resistance characteristics without lowering frequency characteristics and amplification-factor characteristics by forming a partially deep position to a base layer. CONSTITUTION:An N layer 2 is formed on an N type silicon single crystal semiconductor substrate 1. A base layer 3 is formed in the N layer 2, and an emitter layer 4 is formed in the base layer. The projecting sections 32 of base impurity layers partially deeper than other base layer sections 31 are formed to the base layer 3. The projecting sections 32 are formed by diffusing a base several times as doing it twice. Since the titled transistor has such structure, a depletion layer does not extend so much as shown in one-dot chain line 5 when applied voltage between the collector layer 2 and the emitter layer 4 is low, but the depletion layer largely extends as shown in two-dot chain line 6 when applied voltage rises. Accordingly, high dielectric resistance of a large radius of curvature corresponding to the case when the whole base layer is formed in the same depth as the projecting sections is acquired, but passage time is short because carriers pass through the sections 31 of the base layer, and the transistor can respond to an extent up to high frequency.
摘要翻译：目的：通过向基底层形成部分深的位置来获得高介电电阻特性而不降低频率特性和放大系数特性。构成：在N +型硅单晶半导体衬底1上形成N 2层2.在N +层2中形成基极层3，在基底层3上形成发射极层4 层。基底杂质层的突出部分32形成在基底层3上，部分地比其它底层部分31更深。突出部分32通过使基底几次扩散两次而形成。由于标题晶体管具有这样的结构，所以当集电极层2和发射极层4之间的施加电压低时，耗尽层不会像单点划线5所示那样延伸，但是耗尽层大大地延伸，如双点划线6当施加电压上升时。因此，与获取整个基底层相同深度的情况对应的大曲率半径的高介电电阻，但由于载流子通过基底层31的部分，通过时间短，并且晶体管可以响应到高频率的程度。

32. 发明专利

JPS59135765A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59135765A
公开(公告)日：1984-08-04
申请号：JP956783
申请日：1983-01-24
申请人： Nec Corp
发明人： FUNAKOSHI HISASHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To reduce an effect in the lateral direction on the characteristics of a transistor by shallowly setting a central section more than a peripheral region in the junction depth of a base region section. CONSTITUTION:A second conduction type buried region 102 is formed to a first conduction type substrate 101, and an epitaxial layer 103 is formed. A field oxide film 20, one part thereof is bored, and an oxide film 19 are formed to the upper surface of the epitaxial layer 103, and an oxide film 18 is formed in the opening. A first conduction type impurity is introduced to form base regions 120. The thickness of the oxide film 18 is selected so that a region section 15 under the oxide film 18 is formed in a junction shallower than a peripheral region 14 of the region section 15 when the impurity is introduced through a succeeding ion implantation to form the base regions 120. That is, the thickness of the oxide film 18 is set by the relationship of thickness of the oxide film 19 and the nitride film 16. Accordingly, an effect in the lateral direction on the characteristics of a transistor can further be reduced.
摘要翻译：目的：通过在基区部分的结深度上比中心部分更浅地设置周边区域来减小横向对晶体管特性的影响。构成：将第二导电型掩埋区域102形成于第一导电型基板101，形成外延层103。场氧化膜20的一部分被钻孔，并且在外延层103的上表面上形成氧化物膜19，并且在开口中形成氧化物膜18。引入第一导电型杂质以形成基极区域120.选择氧化物膜18的厚度，使得在氧化物膜18下面的区域部分15形成在比区域部分15的周边区域14浅的结点中，通过后续的离子注入引入杂质以形成基极区域120.也就是说，氧化物膜18的厚度由氧化膜19和氮化物膜16的厚度的关系来设定。因此，可以进一步降低横向对晶体管特性的影响。

33. 发明专利

JPS59126670A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59126670A
公开(公告)日：1984-07-21
申请号：JP90083
申请日：1983-01-07
申请人： Nec Corp
发明人： SAKAUCHI HIDEO
IPC分类号： H01L29/73 , H01L21/314 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To prevent the deterioration of withstand voltage and reduce leakage current by providing a phosphorus doped poly Si layer on an insulation film on a collector region, and then protecting the surface thereof with an insulation film. CONSTITUTION:A p type base layer 2 is formed on an n type semiconductor substrate 1 serving as the collector by the impurity diffsion of boron, etc., and further an n type emitter layer 3 is formed in the base layer 2. At the same time of the formation of the emitter, a guard ring 4 of an n type high concentration region is formed. An Si oxide film 5 is formed on the surfaces of the collector 9 and the base region, and the surface of these regions are protected. The Phosphorus doped poly Si layer 6 is formed on the Si oxide film 5, and an insulation film 7 is formed on the surface of the layer 6. Therefore, since the influence by the contamination of ionic substance from the outside can be removed, the deterioration of withstand voltage can be prevented, and the leakage current can be reduced.
摘要翻译：目的：通过在集电区域上的绝缘膜上设置掺磷多晶硅层，然后用绝缘膜保护其表面，防止耐电压劣化，降低漏电流。构成：通过硼等的杂质衍射形成在作为集电体的n型半导体基板1上的p型基极层2，并且在基极层2中还形成有n型发射极层3。形成发射极的时间，形成n型高浓度区域的保护环4。在集电体9和基极区域的表面上形成Si氧化物膜5，并且保护这些区域的表面。在Si氧化物膜5上形成磷掺杂多晶硅层6，在层6的表面上形成绝缘膜7.因此，由于可以除去来自外部的离子物质污染的影响，能够防止耐压劣化，能够降低漏电流。

34. 发明专利

JPS59121872A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59121872A
公开(公告)日：1984-07-14
申请号：JP22103082
申请日：1982-12-15
申请人： Fujitsu Ltd
发明人： WATABE KIYOSHI
IPC分类号： H01L29/872 , H01L21/331 , H01L29/47 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To enable to reduce the size of a semiconductor element in a Schottky diode clamping transistor in which a base electrode and a Schottky diode electrode are commonly used by forming the common electrode of a meta silicide contacted at the side face of the base region. CONSTITUTION:A buried layer 11, an n type epitaxial layer 1, a collector contacting region 4 and a base region 12, in which boron ions are implanted are formed, a dioxidized silicon film 13 on a Schottky diode forming region is removed to open a window, a metal molybdenum film 14 is covered, and heat treated. Then, a molybdenum silicide layer 10 is formed in the Schottky diode forming region covered directly on the surface of the silicon, and the side face and the side face of the base region 12 are vertically connected. Then, the film 14 on the film 13 is removed, arsenic or phosphorus is then implanted, heat treated, and an emitter region 3 is formed. Subsequently, windows are opened at the film 13, and base and Schottky diode electrodes, a collector contacting electrode and an emitter electrode are formed to complete it.
摘要翻译：目的：通过形成在基极侧面接触的间位硅化物的公共电极，能够减小通常使用基极和肖特基二极管电极的肖特基二极管钳位晶体管中的半导体元件的尺寸。构成：形成埋置硼离子的埋层11，n型外延层1，集电极接触区域4和基极区域12，去除肖特基二极管形成区域上的二氧化硅膜13，将金属钼膜14覆盖并进行热处理。然后，在直接覆盖在硅表面上的肖特基二极管形成区域中形成硅化钼层10，并且基极区域12的侧面和侧面垂直连接。然后，除去膜13上的膜14，然后注入砷或磷，进行热处理，形成发射区3。随后，在薄膜13处打开窗口，并且形成基极和肖特基二极管电极，集电极接触电极和发射极电极以完成它。

35. 发明专利

JPS5974670A Lateral transistor 失效
标题翻译：横向晶体管
公开(公告)号：JPS5974670A
公开(公告)日：1984-04-27
申请号：JP18506182
申请日：1982-10-21
申请人： Toshiba Corp
发明人： HIDESHIMA MAKOTO , MURAMOTO KENICHI
IPC分类号： H01L29/417 , H01L21/331 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To enable to realize an element of stable actions and high reliability by a method wherein a conductive layer of the same potential as a base region is so provided on an insulation film on the surface of a substrate as to cover the base region and a p-n junction. CONSTITUTION:N type regions 12 and a collector region 13 are adjacent each other in each direction, the p type base region 11 of a constant width is formed between each region adjacent each other, and the insulation films 14 are formed on the surface, and the conductive layers 16 thereon. These layers 16 are slightly away from mitter electrode parts 18 and a collector electrode part 19, further reach an emitter-base boundary and a collector-base boundary, and are collected to the region 11 through a contact part 15. Insulation layers 17 are formed on these layers 16, and the emitter electrodes 18 and the collector electrode 19 are formed. Thereby, the polarization of the ion mixed into the insulation film or the influence on carriers by an electric field in a common wiring can be prevented, and accordingly the element of stable actions and high reliability can be realized.
摘要翻译：目的：为了能够通过以下方法实现稳定动作和高可靠性的元件：将基底区域具有相同电位的导电层设置在衬底表面上的绝缘膜上以覆盖基底区域，并且 pn结。构成：N个区域12和集电极区域13在各个方向上彼此相邻，在彼此相邻的各个区域之间形成恒定宽度的p型基底区域11，并且在表面上形成绝缘膜14，其上的导电层16。这些层16稍微远离电极部分18和集电极部分19，进一步到达发射极 - 基极边界和集电极 - 基极边界，并通过接触部分15被收集到区域11中。形成绝缘层17 在这些层16上形成发射电极18和集电极19。由此，可以防止混入绝缘膜中的离子的极化或通过公共布线中的电场对载流子的影响，从而可以实现稳定动作和高可靠性的元件。

36. 发明专利

JPS5974669A Bi-directive lateral transistor 失效
标题翻译：双向横向晶体管
公开(公告)号：JPS5974669A
公开(公告)日：1984-04-27
申请号：JP18506082
申请日：1982-10-21
申请人： Toshiba Corp
发明人： HIDESHIMA MAKOTO , MURAMOTO KENICHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To enable to obtain a perfect bi-directivity and a large current by a method wherein a plurality of emitter regions and collector regions are so arranged, on the main surface of a semiconductor substrate serving as a base region, as to be adjacent each other. CONSTITUTION:On the main surface of a base region 23 the N type semiconductor substrate, regions wherein the emitter region 21 and the collector regions 22 of a P type semiconductor respectively of the same size are adjacent each other are so formed in a plurality as to become different each other. Besides, the widths of the regions between adjacent regions are always constant. An emitter electrode wiring 26 and a collector electrode wiring 27 are two parallel wirings rectangular to the regions 21 and 22, and respectively connect each emitter electrode hole 24 and each collector electrode hole 25 opened through insulations films. Such a constitution enables to take a large current by the increase of the amount of transfer of positive holes because of the enlargement of the perimeter of the emitter. The perfect bi-directivity characteristic can be realized from the point that the relation of the emitters and collectors to the base becomes the same to each other completely.
摘要翻译：目的：为了通过如下方式获得完美的双向性和大电流：其中多个发射极区域和集电极区域被布置在作为基极区域的半导体衬底的主表面上，其他。构成：在基极区域23的主表面上，分别具有相同尺寸的P型半导体的发射极区域21和集电极区域22相邻的N型半导体衬底的区域形成为多个，变得彼此不同。此外，相邻区域之间的区域的宽度总是恒定的。发射极电极布线26和集电极布线27是与区域21和22成矩形的两条平行的布线，分别连接通过绝缘膜打开的每个发射极电极孔24和每个集电极孔25。这种结构能够通过由于发射体的周边的扩大而增加正孔的转移量而产生大的电流。从发射器和收集器与基座的关系完全相同的角度可以实现完美的双向性特征。

37. 发明专利

JPS5961177A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5961177A
公开(公告)日：1984-04-07
申请号：JP17124882
申请日：1982-09-30
申请人： Fujitsu Ltd
发明人： MONMA YOSHINOBU
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To form a transistor through self-alignment, in which a manufacturing process is simple and wiring patterning is also easy, in structure called an EEIC (Elevated Electrode IC). CONSTITUTION:An oxide film 21a is formed only on the side of a first polysilicon film 19. The ions of boron, etc. are implanted in order to lower the resistance of an external base under the state to form a base diffusion layer 21, and non-doped polysilicon 22 is covered and the ions of boron B are implanted or boron doped polysilicon is covered. A resist 23 is further applied on these second polysilicon films 22. A second polysilicon film 20 and the resist film 23 are removed so as to be uniformly etched up to the surfaces of the resist 23 and the SiN film 20 formed on the first polysilicon film 19 through ion milling or RIE. The second polysilicon films 22 are oxidized to form an oxide film 24.
摘要翻译：目的：通过自对准形成晶体管，其中制造工艺简单并且布线图案化也容易，在称为EEIC（高架电极IC）的结构中。构成：仅在第一多晶硅膜19的一侧形成氧化物膜21a，为了降低外部基体在该状态下的电阻以形成基极扩散层21，注入硼等的离子，并且未掺杂的多晶硅22被覆盖，硼B的离子被注入或硼掺杂的多晶硅被覆盖。在这些第二多晶硅膜22上进一步施加抗蚀剂23.除去第二多晶硅膜20和抗蚀剂膜23，以均匀地蚀刻到形成在第一多晶硅膜上的抗蚀剂23和SiN膜20的表面 19通过离子铣或RIE。第二多晶硅膜22被氧化以形成氧化膜24。

38. 发明专利

JPS5948957A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS5948957A
公开(公告)日：1984-03-21
申请号：JP15980582
申请日：1982-09-14
申请人： Matsushita Electric Ind Co Ltd
发明人： KAJIYAMA MASAOKI
IPC分类号： H01L29/78 , H01L21/331 , H01L29/417 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To obtain a high speed and large scale IC by a method wherein an emitter and two base electrodes having microscopic width are isolated in excellent reproducibility, their withstand voltage and reliability are properly maintained, and a source and drain is self-matchingly provided for a gate electrode, thereby enabling to reduce the parasitic capacitance. CONSTITUTION:An n layer 42 is buried in a p type Si substrate 4, an n-epitaxial layer 43 is superposed and isolated, and after an n lead out layer 46 has been formed, a window is provided on an oxide film 45 and covered by a polycrystalline Si 48. An oxide film 51 is formed by selectively providing double layer masks of SiO2 49 and Si3N4 50. B-ions are implanted into the layer 48 using the film 51 as a mask, the film 51 is removed, and a thick oxide film 52a, a thin oxide film 52b, a p layer 53 and a p layer 54 are simultaneously formed by performing wet oxidization at low temperature. Said film 52b is removed by etching, a p-base 58 is formed by implanting B ions from an n emitter 57 and then from the same diffusion window 55 using an As-added n polycrystalline Si 56 as a source of diffusion. Subsequently, an electrode is attached as prescribed, and the manufacture of the device is completed. According to this constitution, the IC of high integration and high efficiency can be obtained easily with excellent yield rate of production.
摘要翻译：目的：为了通过以极好的再现性隔离出具有微观宽度的发射极和两个基极的方法获得高速大尺寸IC，其耐压和可靠性被适当地保持，并且源和漏自动匹配栅电极，从而能够减小寄生电容。构成：n +层42被埋在ap型Si衬底4中，n外延层43叠加和隔离，并且在形成n + +引出层46之后，在氧化膜45并被多晶Si 48覆盖。通过选择性地提供SiO 2 49和Si 3 N 4 50的双层掩模形成氧化物膜51.使用膜51作为掩模将B离子注入到层48中，膜51 并且通过在低温下进行湿氧化同时形成厚氧化膜52a，薄氧化物膜52b，p ++层53和ap + +层54。通过蚀刻去除所述膜52b，通过从n +发射体57注入B离子，然后使用As加入的n +多晶Si 56作为源来从相同的扩散窗55形成p基底58 的扩散。接着，按规定安装电极，完成装置的制造。根据该结构，能够以优异的制造成品率容易地获得高集成度，高效率的IC。

39. 发明专利

JPS5947763A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5947763A
公开(公告)日：1984-03-17
申请号：JP15812082
申请日：1982-09-13
申请人： Hitachi Ltd
发明人： MIYAZAKI TAKAO , KAGAMI JIYUNICHIROU , KASHIYUU NOBUYOSHI , KATSUEDA MINEO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To contrive to make uniform the distributions of emitter current and chip temperature by a method wherein the inside of each emitter stripe is finely divided, resulting in the formation of ballast resistance in the form of distribution constant, in a semiconductor device provided with a multi emitter transistor. CONSTITUTION:Each stripe of a high output transistor consisting of a plurality of emitter stripes (e) is divided into five fine pieces for convenience. For the purpose of distributing the consumed power density at each part of the emitter fine piece, REi determined by the formula REi=0.0025.VCE.mui from the thermal resistance value mu1 at each part in the chip and external impressed voltage VCE is added to each emitter emitter fine piece as the ballast resistance. When the power density added to each fine piece is distributed, the temperature distribution becomes uniform, accordingly, the breakdown of the transistor is prevented by heat runaway, and the uniformity of the current distribution of the emitter fine piece improves; therefore the high frequency performance also improves.
摘要翻译：目的：通过一种方法使发射极电流和芯片温度的分布均匀化，其中每个发射极条的内部细分，导致在分布常数形式中形成镇流电阻，在设置有多发射极晶体管。构成：为了方便起见，将由多个发射极条（e）组成的高输出晶体管的每个条纹分成五个细片。为了在发射极细片的每个部分分配消耗的功率密度，将由公式REi = 0.0025.VCE.mui确定的REi与芯片中每个部分的热阻值mu1和外部外加电压VCE相加每个发射极发射极细片作为镇流电阻。当分散到每个细片上的功率密度分布时，温度分布变得均匀，因此通过热失控来防止晶体管的击穿，并且发射极细片的电流分布的均匀性提高; 因此高频性能也提高。

40. 发明专利

JPS5946064A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5946064A
公开(公告)日：1984-03-15
申请号：JP15701882
申请日：1982-09-09
申请人： Toshiba Corp
发明人： SHIMIZU YASUO , HOSOMI SADASHIGE
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To improve the hFE-Ic characteristic by a method wherein a base region is left inside an emitter region while the electrode on the base region outside the emitter region and the other electrode on the base region inside the emitter region are supplied with the same potential. CONSTITUTION:A circular emitter region E is formed in a base region B1 on the overall surface of a collector region C leaving a partial region B2 of B1 around the central part of the base region B1. A circular electrode B'1 is provided on the B1 and another electrode B'2 is provided on the central part of B2 and the B'1 and the B'2 are joined by an Al overray wiring 30 making them keep the same potential. Another electrode E' is provided on the overall surface of the emitter region E. In such a constitution, the overall length of EB junction equals to the total of the outside junction 31 and the inside junction 32 to be extended considerably improving the hFE-Ic characteristics. In other words, the miniaturization of emitter pattern to specify the length of EB junction may be relieved eliminating most of the influence effecting upon the safety operation region.
摘要翻译：目的：为了提高hFE-1c特性，其中基极区域位于发射极区域内，而在发射极区域外部的基极区域上的电极和发射极区域内的基极区域上的另一个电极被提供相同的方法潜在。构成：在集电区域C的整个表面上的基极区域B1中形成圆形发射极区域E，在基极区域B1的中心部分附近存在B1的部分区域B2。在B1上设置圆形电极B'1，在B2的中心部分设置另一个电极B'2，B'1和B'2由Al突出布线30连接起来使得它们保持相同的电位。另外的电极E'设置在发射区E的整个表面上。在这种结构中，EB结的总长度等于外部结31和内部结32的总长度，以显着地改善hFE-Ic 特点。换句话说，可以减轻用于指定EB结长度的发射极图案的小型化，从而消除了影响安全操作区域的大部分影响。

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